Invention Grant
- Patent Title: Wafer level integrated MEMS device enabled by silicon pillar and smart cap
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Application No.: US16584752Application Date: 2019-09-26
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Publication No.: US10961118B2Publication Date: 2021-03-30
- Inventor: Yi-Chia Lee , Chin-Min Lin , Cheng San Chou , Hsiang-Fu Chen , Wen-Chuan Tai , Ching-Kai Shen , Hua-Shu Ivan Wu , Fan Hu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: B81C1/00
- IPC: B81C1/00 ; B81B7/02

Abstract:
The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. In some embodiments, a ventilation trench and an isolation trench are concurrently within a capping substrate. The isolation trench isolates a silicon region and has a height substantially equal to a height of the ventilation trench. A sealing structure is formed within the ventilation trench and the isolation trench, the sealing structure filing the isolation trench and defining a vent within the ventilation trench. A device substrate is provided and bonded to the capping substrate at a first gas pressure and hermetically sealing a first cavity associated with a first MEMS device and a second cavity associated with a second MEMS device. The capping substrate is thinned to open the vent to adjust a gas pressure of the second cavity.
Public/Granted literature
- US20200024137A1 WAFER LEVEL INTEGRATED MEMS DEVICE ENABLED BY SILICON PILLAR AND SMART CAP Public/Granted day:2020-01-23
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