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公开(公告)号：US20200024137A1
公开(公告)日：2020-01-23
申请号：US16584752
申请日：2019-09-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Chia Lee , Chin-Min Lin , Cheng San Chou , Hsiang-Fu Chen , Wen-Chuan Tai , Ching-Kai Shen , Hua-Shu Ivan Wu , Fan Hu
Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. In some embodiments, a ventilation trench and an isolation trench are concurrently within a capping substrate. The isolation trench isolates a silicon region and has a height substantially equal to a height of the ventilation trench. A sealing structure is formed within the ventilation trench and the isolation trench, the sealing structure filing the isolation trench and defining a vent within the ventilation trench. A device substrate is provided and bonded to the capping substrate at a first gas pressure and hermetically sealing a first cavity associated with a first MEMS device and a second cavity associated with a second MEMS device. The capping substrate is thinned to open the vent to adjust a gas pressure of the second cavity.
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公开(公告)号：US10131540B2
公开(公告)日：2018-11-20
申请号：US14645650
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shao-Chi Yu , Chia-Ming Hung , Hsin-Ting Huang , Hsiang-Fu Chen , Allen Timothy Chang , Wen-Chuan Tai
Abstract: The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.
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公开(公告)号：US20170233249A1
公开(公告)日：2017-08-17
申请号：US15585805
申请日：2017-05-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsin-Ting Huang , Hsiang-Fu Chen , Wen-Chuan Tai , Shao-Chi Yu , Chia-Ming Hung , Allen Timothy Chang , Bruce C.S. Chou , Chin-Min Lin
CPC classification number: B81C1/00285 , B81B7/02 , B81B2201/0235 , B81B2201/0242 , B81B2207/095 , B81B2207/096 , B81C2203/0145
Abstract: The present disclosure relates to a method of forming a micro-electro mechanical system (MEMs) structure. In some embodiments, the method may be performed by providing a device substrate having a first MEMS device and a second MEMS device, and by providing a capping structure having a first cavity and a second cavity. The capping structure is bonded to the device substrate, such that the first cavity is arranged over the first MEMS device and the second cavity is arranged over the second MEMS device. A first pressure is established within the first cavity and the second cavity. A vent is selectively etched within the capping structure to change the first pressure within the second cavity to a second pressure, which is different from the first pressure.
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公开(公告)号：US11365115B2
公开(公告)日：2022-06-21
申请号：US16558539
申请日：2019-09-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fan Hu , Chun-Ren Cheng , Hsiang-Fu Chen , Wen-Chuan Tai
Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.
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公开(公告)号：US11289568B2
公开(公告)日：2022-03-29
申请号：US16410259
申请日：2019-05-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chi-Yuan Shih , Kai-Fung Chang , Shih-Fen Huang , Wen-Chuan Tai , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Anderson Lin , Fu-Chun Huang , Chun-Ren Cheng , Ivan Hua-Shu Wu , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.
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Patent Agency Ranking
公开(公告)号：US10961118B2
公开(公告)日：2021-03-30
申请号：US16584752
申请日：2019-09-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Chia Lee , Chin-Min Lin , Cheng San Chou , Hsiang-Fu Chen , Wen-Chuan Tai , Ching-Kai Shen , Hua-Shu Ivan Wu , Fan Hu
Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. In some embodiments, a ventilation trench and an isolation trench are concurrently within a capping substrate. The isolation trench isolates a silicon region and has a height substantially equal to a height of the ventilation trench. A sealing structure is formed within the ventilation trench and the isolation trench, the sealing structure filing the isolation trench and defining a vent within the ventilation trench. A device substrate is provided and bonded to the capping substrate at a first gas pressure and hermetically sealing a first cavity associated with a first MEMS device and a second cavity associated with a second MEMS device. The capping substrate is thinned to open the vent to adjust a gas pressure of the second cavity.
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公开(公告)号：US20200346923A1
公开(公告)日：2020-11-05
申请号：US16934255
申请日：2020-07-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Chuan Tai , Fan Hu
Abstract: The present disclosure relates to a MEMS package having different trench depths, and a method of fabricating the MEMS package. In some embodiments, a cap substrate is bonded to a device substrate. The cap substrate comprises a first trench, a second trench, and an edge trench recessed from at a front-side surface of the cap substrate. A stopper is disposed within the first trench and raised from a bottom surface of the first trench. The stopper has a top surface lower than the front-side surface of the cap substrate.
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公开(公告)号：US20190161346A1
公开(公告)日：2019-05-30
申请号：US15823969
申请日：2017-11-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Chia Lee , Chin-Min Lin , Cheng San Chou , Hsiang-Fu Chen , Wen-Chuan Tai , Ching-Kai Shen , Hua-Shu Ivan Wu , Fan Hu
Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. A device substrate comprising first and second MEMS devices is bonded to a capping substrate comprising first and second recessed regions. A ventilation trench is laterally spaced apart from the recessed regions and within the second cavity. A sealing structure is arranged within the ventilation trench and defines a vent in fluid communication with the second cavity. A cap is arranged within the vent to seal the second cavity at a second gas pressure that is different than a first gas pressure of the first cavity.
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公开(公告)号：US20190161342A1
公开(公告)日：2019-05-30
申请号：US15822538
申请日：2017-11-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Chuan Tai , Fan Hu
Abstract: The present disclosure relates to a MEMS package having a cap substrate with different trench depths, and a method of fabricating the MEMS package. In some embodiments, a first trench in a first device region and a scribe trench in a scribe line region are formed at a front side of a cap substrate. Then, a hard mask is formed and patterned over the cap substrate. Then, with the hard mask in place, an etch is performed to the cap substrate such that an uncovered portion of a bottom surface of the first trench is recessed while a covered portion of the bottom surface of the first trench is non-altered to form a stopper within the first trench. Then, the front side of the cap substrate is bonded to a device substrate, enclosing the first trench over a first MEMS device.
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10.发明申请STRUCTURE AND METHOD TO MITIGATE SOLDERING OFFSET FOR WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) APPLICATIONS 审中-公开用于降低水平芯片尺寸封装（WLCSP）应用的焊接偏移的结构和方法公开(公告)号：US20160264402A1
公开(公告)日：2016-09-15
申请号：US14645650
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shao-Chi Yu , Chia-Ming Hung , Hsin-Ting Huang , Hsiang-Fu Chen , Allen Timothy Chang , Wen-Chuan Tai
CPC classification number: B81C1/0023 , B81B7/0048 , B81B7/0051 , B81B7/0054 , B81B7/007 , H01L2224/04026 , H01L2224/05624 , H01L2224/05644 , H01L2224/16225 , H01L2224/2957 , H01L2224/29624 , H01L2224/29644
Abstract: The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.
Abstract translation: 本公开涉及一种具有应力吸收帽基片的晶片级芯片级封装（WLCSP）。 盖基板通过结合环和布置在盖基板的上表面上的接合焊盘接合到管芯。 贯穿衬底通孔（TSV）从接合焊盘延伸穿过盖衬底到帽衬底的下表面。 此外，上表面中的凹槽围绕接合焊盘延伸并且沿着接合环的侧壁延伸。 凹槽吸收诱发的应力，从而减轻模具中的任何装置偏移。
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