Invention Grant
- Patent Title: Gate structure and method with dielectric gates and gate-cut features
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Application No.: US16853474Application Date: 2020-04-20
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Publication No.: US10998237B2Publication Date: 2021-05-04
- Inventor: Ta-Chun Lin , Buo-Chin Hsu , Kuo-Hua Pan , Jhon Jhy Liaw , Chih-Yung Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L21/311 ; H01L29/66 ; H01L21/3105

Abstract:
A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.
Public/Granted literature
- US20200243396A1 Gate Structure and Method Public/Granted day:2020-07-30
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