Invention Grant
- Patent Title: Stacked transistor assembly with dual middle mounting clips
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Application No.: US16675525Application Date: 2019-11-06
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Publication No.: US11075148B2Publication Date: 2021-07-27
- Inventor: Jeffrey Peter Gambino , David T. Price , Jeffery A. Neuls , Dean E. Probst , Santosh Menon , Peter A. Burke , Bigildis Dosdos
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Brake Hughes Bellermann LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/495 ; H01L25/00 ; H01L25/11

Abstract:
A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.
Public/Granted literature
- US20210111106A1 STACKED TRANSISTOR ASSEMBLY WITH DUAL MIDDLE MOUNTING CLIPS Public/Granted day:2021-04-15
Information query
IPC分类: