Invention Grant
- Patent Title: High performance interconnect physical layer
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Application No.: US16835241Application Date: 2020-03-30
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Publication No.: US11080212B2Publication Date: 2021-08-03
- Inventor: Venkatraman Iyer , Darren S. Jue , Jeff Willey , Robert G. Blankenship
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F13/16 ; G06F1/12 ; G06F13/40 ; H04L12/933 ; H04L12/741

Abstract:
A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
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