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公开(公告)号:US12189550B2
公开(公告)日:2025-01-07
申请号:US18347236
申请日:2023-07-05
Applicant: Intel Corporation
Inventor: Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/77 , G06F9/30 , G06F9/445 , G06F9/46 , G06F11/10 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/40 , G06F13/42 , H04L9/06 , H04L49/15 , G06F8/73 , H04L12/46 , H04L45/74
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号:US10248591B2
公开(公告)日:2019-04-02
申请号:US15393153
申请日:2016-12-28
Applicant: Intel Corporation
Inventor: Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert H. Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , H04L12/933 , G06F9/46 , G06F13/40 , G06F12/0813 , G06F12/0815 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L12/741 , G06F8/73 , H04L12/46
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号:US10216661B2
公开(公告)日:2019-02-26
申请号:US15821401
申请日:2017-11-22
Applicant: Intel Corporation
Inventor: Venkatraman Iyer , Darren S. Jue , Rahul Shah , Arvind Kumar
IPC: G06F9/30 , G06F13/22 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F12/0806 , H04L12/933 , G06F9/46 , G06F13/40 , G06F12/0813 , G06F12/0815 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L12/741 , G06F8/73 , H04L12/46
Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.
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公开(公告)号:US10146733B2
公开(公告)日:2018-12-04
申请号:US15167461
申请日:2016-05-27
Applicant: Intel Corporation
Inventor: Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Debendra Das Sharma , Jeffrey C. Swanson
Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
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公开(公告)号:US09697158B2
公开(公告)日:2017-07-04
申请号:US14538919
申请日:2014-11-12
Applicant: INTEL CORPORATION
Inventor: Venkatraman Iyer , Darren S. Jue , Jeff Willey , Robert G. Blankenship
IPC: G06F1/12 , G06F13/40 , G06F13/42 , H04L12/933 , H04L12/741
CPC classification number: G06F13/161 , G06F1/12 , G06F13/1673 , G06F13/4004 , G06F13/4068 , G06F13/4221 , H04L45/74 , H04L49/15
Abstract: A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.
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公开(公告)号:US20170116148A1
公开(公告)日:2017-04-27
申请号:US15393366
申请日:2016-12-29
Applicant: Intel Corporation
Inventor: Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer
CPC classification number: G06F13/4004 , G06F13/4221 , G06N99/005 , Y02D10/14 , Y02D10/151
Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.
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公开(公告)号:US20220114122A1
公开(公告)日:2022-04-14
申请号:US17556853
申请日:2021-12-20
Applicant: Intel Corporation
Inventor: Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号:US11269793B2
公开(公告)日:2022-03-08
申请号:US16937499
申请日:2020-07-23
Applicant: Intel Corporation
Inventor: Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L45/74 , G06F8/73 , H04L12/46
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号:US10606774B2
公开(公告)日:2020-03-31
申请号:US15851705
申请日:2017-12-21
Applicant: Intel Corporation
Inventor: Venkatraman Iyer , Darren S. Jue , Jeff Willey , Robert G. Blankenship
IPC: G06F1/12 , G06F13/42 , H04L5/00 , G06F13/16 , G06F13/40 , H04L12/933 , H04L12/741
Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
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公开(公告)号:US10380046B2
公开(公告)日:2019-08-13
申请号:US15918895
申请日:2018-03-12
Applicant: Intel Corporation
Inventor: Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Ashish Gupta
IPC: G06F13/22 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F12/0813 , G06F12/0815 , G06F9/445 , G06F11/10 , H04L9/06 , G06F1/3287 , H04L12/933 , G06F12/0808 , G06F8/73 , H04L12/46 , H04L12/741
Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.
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