Invention Grant
- Patent Title: Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies
-
Application No.: US16547885Application Date: 2019-08-22
-
Publication No.: US11081497B2Publication Date: 2021-08-03
- Inventor: Shyam Surthi , Richard J. Hill , Byeung Chul Kim , Akira Goda
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/11556
- IPC: H01L27/11556 ; H01L27/11582 ; H01L29/51 ; H01L29/792 ; H01L21/28 ; H01L29/49 ; H01L29/788

Abstract:
Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.
Public/Granted literature
Information query
IPC分类: