公开(公告)号：US12068255B2

公开(公告)日：2024-08-20

申请号：US17399283

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  John D. Hopkins ,  Richard J. Hill ,  Indra V. Chary ,  Kar Wui Thong

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H10B41/27 ,  H10B43/27

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region. Other memory arrays and methods are disclosed.

公开(公告)号：US20240274533A1

公开(公告)日：2024-08-15

申请号：US18416227

申请日：2024-01-18

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp ,  Richard J. Hill

IPC: H01L23/528 ,  G11C5/06 ,  G11C16/04 ,  H01L21/762 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L23/5283 ,  G11C5/063 ,  G11C16/0483 ,  H01L21/76224 ,  H01L25/0657 ,  H01L27/0922 ,  H01L29/0649 ,  H01L2225/06524

Abstract: A semiconductor device assembly including a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines being connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding string driver, wherein a backside surface of the first wafer is bonded to a frontside surface of the second wafer to form a wafer-on-wafer (WOW) bonding.

公开(公告)号：US11903196B2

公开(公告)日：2024-02-13

申请号：US17127971

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Matthew J. King ,  Sidhartha Gupta ,  Paolo Tessariol ,  Kunal Shrotri ,  Kye Hyun Baek ,  Kyle A. Ritter ,  Shuji Tanaka ,  Umberto Maria Meotto ,  Richard J. Hill ,  Matthew Holland

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230397422A1

公开(公告)日：2023-12-07

申请号：US17884299

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  David H. Wells ,  Byeung Chul Kim ,  Richard J. Hill ,  Paolo Tessariol

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: Methods, systems, and devices for merged cavities and buried etch stops for three-dimensional memory arrays are described. For example, a row of cavities may be formed using a cavity etching process and material separating cavities of the row may be removed to merge the row of cavities to form a trench. In some cases, a trench may be formed from multiple rows of cavities. Additionally, or alternatively, a trench may be formed from a pattern of cavities that includes different quantities of rows at different locations along the trench. In some examples, etch stopping material portions (e.g., etch stops) may be formed at locations corresponding to cavities prior to the cavity etching process. For example, exposed material surfaces at locations corresponding to cavities or trenches may be oxidized to form etch stops.

公开(公告)号：US11690210B2

公开(公告)日：2023-06-27

申请号：US16728492

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Vladimir Machkaoutsan ,  Richard J. Hill

IPC: H01L27/108 ,  G11C11/402 ,  G11C11/404

CPC classification number: H01L27/10805 ,  G11C11/4023 ,  G11C11/4045 ,  H01L27/10847

Abstract: Disclosed are monolithically integrated three-dimensional (3D) DRAM array structures that include one-transistor, one-capacitor (1T1C) cells embedded at multiple device tiers of a layered substrate assembly. In some embodiments, vertical electrically conductive data-line and ground pillars extending through the substrate assembly provide the transistor source and ground voltages, and horizontal electrically conductive access lines at multiple device levels provide the transistor gate voltages. Process flows for fabricating the 3D DRAM arrays are also described.

公开(公告)号：US11640837B2

公开(公告)日：2023-05-02

申请号：US17397028

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Richard J. Hill ,  Aaron Michael Lowe

IPC: G11C7/18 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.

公开(公告)号：US20230065142A1

公开(公告)日：2023-03-02

申请号：US17968651

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C5/06 ,  H01L21/50 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11587948B2

公开(公告)日：2023-02-21

申请号：US17369605

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US11557608B2

公开(公告)日：2023-01-17

申请号：US17393664

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/792 ,  H01L21/02 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US11514953B2

公开(公告)日：2022-11-29

申请号：US17243937

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C11/34 ,  G11C5/06 ,  H01L21/50 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.