公开(公告)号：US20240130124A1

公开(公告)日：2024-04-18

申请号：US18324068

申请日：2023-05-25

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC分类号： H10B43/27

CPC分类号： H10B43/27

摘要： An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20230034157A1

公开(公告)日：2023-02-02

申请号：US17389864

申请日：2021-07-30

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Davide Resnati ,  Gianpietro Carnevale ,  Shyam Surthi

IPC分类号： H01L27/11582

摘要： Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220077176A1

公开(公告)日：2022-03-10

申请号：US17013047

申请日：2020-09-04

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC分类号： H01L27/11582

摘要： An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20210057434A1

公开(公告)日：2021-02-25

申请号：US16547885

申请日：2019-08-22

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US10707211B2

公开(公告)日：2020-07-07

申请号：US16139816

申请日：2018-09-24

申请人： Micron Technology, Inc.

发明人： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC分类号： H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L21/822

摘要： Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

公开(公告)号：US12082416B2

公开(公告)日：2024-09-03

申请号：US17389864

申请日：2021-07-30

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Davide Resnati ,  Gianpietro Carnevale ,  Shyam Surthi

IPC分类号： H10B43/27

CPC分类号： H10B43/27

摘要： Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230397422A1

公开(公告)日：2023-12-07

申请号：US17884299

申请日：2022-08-09

申请人： Micron Technology, Inc.

发明人： Yoshiaki Fukuzumi ,  David H. Wells ,  Byeung Chul Kim ,  Richard J. Hill ,  Paolo Tessariol

IPC分类号： H01L27/11582

CPC分类号： H01L27/11582

摘要： Methods, systems, and devices for merged cavities and buried etch stops for three-dimensional memory arrays are described. For example, a row of cavities may be formed using a cavity etching process and material separating cavities of the row may be removed to merge the row of cavities to form a trench. In some cases, a trench may be formed from multiple rows of cavities. Additionally, or alternatively, a trench may be formed from a pattern of cavities that includes different quantities of rows at different locations along the trench. In some examples, etch stopping material portions (e.g., etch stops) may be formed at locations corresponding to cavities prior to the cavity etching process. For example, exposed material surfaces at locations corresponding to cavities or trenches may be oxidized to form etch stops.

公开(公告)号：US20230189515A1

公开(公告)日：2023-06-15

申请号：US17549237

申请日：2021-12-13

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Shyam Surthi

IPC分类号： H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/538

CPC分类号： H01L27/11556 ,  G11C5/025 ,  H01L27/11582 ,  H01L23/5386

摘要： A microelectronic device comprises a stack structure, a staircase structure, an etch stop material, and insulative material. The stack structure comprises conductive structures, and air gaps vertically alternating with the conductive structures. The staircase structure is within the stack structure and has steps comprising edges of at least some of the conductive structures of the stack structure. The etch stop material continuously extends over the conductive structures and at least partially defines horizontal boundaries of the air gaps. The insulative material overlies the etch stop material. Additional microelectronic devices, memory devices, electronic systems, and methods are also disclosed.

公开(公告)号：US11587948B2

公开(公告)日：2023-02-21

申请号：US17369605

申请日：2021-07-07

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US11557608B2

公开(公告)日：2023-01-17

申请号：US17393664

申请日：2021-08-04

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/792 ,  H01L21/02 ,  H01L29/788

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.