Invention Grant
- Patent Title: Vertical FET with symmetric junctions
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Application No.: US16441640Application Date: 2019-06-14
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Publication No.: US11094798B2Publication Date: 2021-08-17
- Inventor: Lan Yu , Xin Miao , Chen Zhang , Heng Wu , Kangguo Cheng
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agent L. Jeffrey Kelly
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/66 ; H01L29/40 ; H01L21/324 ; H01L29/78

Abstract:
An embodiment of the invention may include a method of forming a semiconductor structure, and the resulting semiconductor structure. The method may include removing a gate region from a layered stack located on a source/drain layer. The layered stack includes a first spacer located on the source drain layer, a dummy layer located on the first spacer, and a second spacer located on the dummy layer. The method may include forming a channel material above the source/drain layer in the gate region. The method may include forming a top source/drain on the channel material. The method may include forming a hardmask surrounding the top source/drain. The method may include removing a portion of the layered stack that is not beneath the hardmask.
Information query
IPC分类: