公开(公告)号：US12002874B2

公开(公告)日：2024-06-04

申请号：US17384908

申请日：2021-07-26

申请人： International Business Machines Corporation

发明人： Junli Wang ,  Ruilong Xie ,  Brent Anderson ,  Chen Zhang ,  Heng Wu

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7851

摘要： A semiconductor structure includes a power rail contact at least partially disposed between a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure. The power rail contact is in contact with a buried power rail disposed under the first and second vertical fin structures. The power rail contact is in contact with at least one of the first and second source/drain regions. A contact cap is disposed above the power rail contact.

公开(公告)号：US20240128333A1

公开(公告)日：2024-04-18

申请号：US17967428

申请日：2022-10-17

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Julien Frougier ,  Chen Zhang ,  Min Gyu Sung ,  Heng Wu

IPC分类号： H01L29/417 ,  H01L21/762 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/41733 ,  H01L21/76283 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L23/5286

摘要： A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.

公开(公告)号：US20240072047A1

公开(公告)日：2024-02-29

申请号：US17900047

申请日：2022-08-31

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Julien Frougier ,  Brent A. Anderson ,  Chen Zhang

IPC分类号： H01L27/088 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L27/088 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/78696

摘要： A semiconductor structure is provided that includes a first pair of stacked devices located in a first active device region and a second pair of stacked devices located in a second active device region. Each stacked device of the pair of stacked devices includes a second field effect transistor (FET) stacked over a first FET, and within each active device region the pair of stacked devices is separated by an inter-device dielectric pillar. A local interconnect structure is located in a non-active device region that is positioned between the first and second active device regions. The local interconnect structure can be connected to a back side power rail and a source/drain region of one of the second FETs, or connected to a front side signal line and a source/drain region of one of the first FETs.

公开(公告)号：US20240014322A1

公开(公告)日：2024-01-11

申请号：US18473482

申请日：2023-09-25

申请人： International Business Machines Corporation

发明人： Sung Dae Suk ,  Somnath Ghosh ,  Chen Zhang ,  Junli Wang ,  Devendra K. Sadana ,  Dechao Guo

IPC分类号： H01L29/78 ,  H01L25/07 ,  H01L29/08

CPC分类号： H01L29/785 ,  H01L29/7827 ,  H01L25/074 ,  H01L29/0847

摘要： A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

公开(公告)号：US20240014135A1

公开(公告)日：2024-01-11

申请号：US17860082

申请日：2022-07-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Junli Wang ,  Albert M. Chu ,  Albert M. Young ,  Chen Zhang ,  Su Chen Fan ,  Ruilong Xie

IPC分类号： H01L23/528 ,  H01L23/48 ,  H01L21/8234 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L23/481 ,  H01L21/823475 ,  H01L29/78696

摘要： A semiconductor device including a first source/drain region (S/D) located on a frontside of a substrate, wherein the first source/drain region has a first width, a second S/D region located on the frontside of the substrate, wherein the second source/drain region is located above the first source drain region, wherein the second source/drain region has second width, wherein the first width is larger than the second width, a first power rail located on a backside of the substrate, a second power rail located on the backside of the substrate, a first connector in contact with the first source/drain region, wherein the first connector is only in contact with a sidewall of the first source/drain region, and a second connector in contact with the second source/drain region, wherein the second connector is in contact with a top surface and a side surface of the second source/drain region.

公开(公告)号：US20230420458A1

公开(公告)日：2023-12-28

申请号：US17847765

申请日：2022-06-23

申请人： International Business Machines Corporation

发明人： Joshua M. Rubin ,  Chen Zhang ,  Tenko Yamashita ,  Brent A. Anderson

IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66 ,  H01L21/822 ,  H01L21/8238

CPC分类号： H01L27/0922 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/78642 ,  H01L29/66742 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/823885

摘要： A plurality of transistor components, a system, and a method of forming a vertically stacked transistor structure within a wafer. The plurality of transistor components may include a first bottom transistor, where the first bottom transistor includes a channel, a gate, a source, and a drain. The plurality of transistor components may also include a first contact on top of the first bottom transistor, where the first contact is proximately connected to the first bottom transistor. The plurality of transistor components may also include a first set of stacked transistors, where the first set of stacked transistors includes a second top transistor on top of a second bottom transistor.

公开(公告)号：US20230299205A1

公开(公告)日：2023-09-21

申请号：US17655371

申请日：2022-03-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Heng Wu ,  Julien Frougier ,  Ruilong Xie ,  Chen Zhang

IPC分类号： H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/78642 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78618

摘要： A semiconductor structure including a bottom source drain region arranged above front-end-of-line circuitry, a gate region disposed above and insulated from the bottom source drain region, a top source drain region disposed above and insulated from the gate region, and a channel region adjacent to the gate region and extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.

公开(公告)号：US11764259B2

公开(公告)日：2023-09-19

申请号：US17384307

申请日：2021-07-23

申请人： International Business Machines Corporation

发明人： Chen Zhang ,  Tenko Yamashita ,  Xin Miao ,  Wenyu Xu ,  Kangguo Cheng

IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/0649 ,  H01L29/41741 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.

公开(公告)号：US11757036B2

公开(公告)日：2023-09-12

申请号：US17388572

申请日：2021-07-29

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Chen Zhang ,  Julien Frougier ,  Alexander Reznicek ,  Shogo Mochizuki

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6653 ,  H01L29/66666

摘要： A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

公开(公告)号：US11705517B2

公开(公告)日：2023-07-18

申请号：US17136185

申请日：2020-12-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Xin Miao ,  Kangguo Cheng ,  Wenyu Xu ,  Chen Zhang

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/762 ,  H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308

CPC分类号： H01L29/7843 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116

摘要： A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.