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公开(公告)号：US12108692B2
公开(公告)日：2024-10-01
申请号：US17473359
申请日：2021-09-13
发明人： Heng Wu , Tian Shen , Kevin W. Brew , Jingyun Zhang
CPC分类号： H10N70/253 , H10N70/063 , H10N70/231 , H10N70/823 , H10N70/8413 , H10N70/8828
摘要： A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.
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公开(公告)号：US12002874B2
公开(公告)日：2024-06-04
申请号：US17384908
申请日：2021-07-26
发明人： Junli Wang , Ruilong Xie , Brent Anderson , Chen Zhang , Heng Wu
IPC分类号： H01L29/66 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/823431 , H01L27/0886 , H01L29/7851
摘要： A semiconductor structure includes a power rail contact at least partially disposed between a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure. The power rail contact is in contact with a buried power rail disposed under the first and second vertical fin structures. The power rail contact is in contact with at least one of the first and second source/drain regions. A contact cap is disposed above the power rail contact.
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3.发明公开公开(公告)号：US20240172454A1
公开(公告)日：2024-05-23
申请号：US18057836
申请日：2022-11-22
发明人： Julien Frougier , Ruilong Xie , Kangguo Cheng , Heng Wu , Min Gyu Sung , Chanro Park
CPC分类号： H01L27/228 , H01L27/11502 , H01L27/2454 , H01L45/04 , H03K19/1733 , H03K19/20
摘要： Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.
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公开(公告)号：US11990530B2
公开(公告)日：2024-05-21
申请号：US18317165
申请日：2023-05-15
发明人： Jingyun Zhang , Choonghyun Lee , Chun Wing Yeung , Robin Hsin Kuo Chao , Heng Wu
IPC分类号： H01L21/02 , H01L21/306 , H01L21/3065 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66522 , H01L21/02532 , H01L21/02546 , H01L21/02609 , H01L21/3065 , H01L29/42392 , H01L29/66469 , H01L29/6653 , H01L29/78696 , H01L29/66545
摘要： Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.
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公开(公告)号：US20240128333A1
公开(公告)日：2024-04-18
申请号：US17967428
申请日：2022-10-17
发明人： Ruilong Xie , Julien Frougier , Chen Zhang , Min Gyu Sung , Heng Wu
IPC分类号： H01L29/417 , H01L21/762 , H01L29/40 , H01L29/66 , H01L29/775
CPC分类号： H01L29/41733 , H01L21/76283 , H01L29/401 , H01L29/66439 , H01L29/66742 , H01L29/775 , H01L23/5286
摘要： A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.
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公开(公告)号：US20240063189A1
公开(公告)日：2024-02-22
申请号：US17820264
申请日：2022-08-17
发明人： Heng Wu , Ruilong Xie , Julien Frougier , Min Gyu Sung , Nicolas Jean Loubet
IPC分类号： H01L25/07 , H01L21/822 , H01L21/84 , H01L27/12 , H01L27/06 , H01L29/786
CPC分类号： H01L25/074 , H01L21/8221 , H01L21/845 , H01L27/1211 , H01L27/0688 , H01L29/78696
摘要： A long channel transistor structure including a first transistor array adjacent to a second transistor array, a third transistor array adjacent to a fourth transistor array, where the third transistor array and the fourth transistor array are arranged above the first transistor array and the second transistor array, and a continuous channel path through channels of the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.
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公开(公告)号：US20230420502A1
公开(公告)日：2023-12-28
申请号：US17808124
申请日：2022-06-22
发明人： Heng Wu , Junli Wang , Ruilong Xie , Albert M. Young , Albert M. Chu , Brent A. Anderson , Ravikumar Ramachandran
IPC分类号： H01L29/06 , H01L29/786 , H01L29/775 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/0673 , H01L29/78618 , H01L29/78696 , H01L29/775 , H01L29/66439 , H01L21/823412 , H01L21/823418
摘要： A field effect transistor (“FET”) stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.
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公开(公告)号：US20230378259A1
公开(公告)日：2023-11-23
申请号：US17664082
申请日：2022-05-19
发明人： Ruilong Xie , Heng Wu , Julien Frougier , Min Gyu Sung
IPC分类号： H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/0665 , H01L29/42392 , H01L29/78618 , H01L29/78696 , H01L29/66742 , H01L21/823412 , H01L21/823418 , H01L29/66545
摘要： Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet and adjacent source/drain regions are provided, where a dummy gate having a gate cut straddles over the nanosheet stack. A semiconductor layer is wafer bonded. A fin is patterned in the semiconductor layer. A source/drain region is formed. A spacer is formed on the bottom source/drain region. A dummy gate is formed on sidewalls of a portion of the fin. A source/drain region is formed. A trench is formed that passes through one dummy gate to the other dummy gate. The dummy gates are removed. Each sacrificial semiconductor material nanosheet is removed. Functional gate structures are formed in regions occupied by the dummy gates and each sacrificial semiconductor material nanosheet.
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公开(公告)号：US20230360971A1
公开(公告)日：2023-11-09
申请号：US17662436
申请日：2022-05-09
发明人： Heng Wu , Ruilong Xie , Albert M. Chu , Albert M. Young , Junli Wang , Brent A. Anderson
IPC分类号： H01L21/768 , H01L23/48 , H01L29/417
CPC分类号： H01L21/76895 , H01L23/481 , H01L21/76897 , H01L29/41775 , H01L24/32
摘要： Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.
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公开(公告)号：US20230299205A1
公开(公告)日：2023-09-21
申请号：US17655371
申请日：2022-03-18
发明人： Heng Wu , Julien Frougier , Ruilong Xie , Chen Zhang
IPC分类号： H01L29/786 , H01L29/417 , H01L29/66
CPC分类号： H01L29/78642 , H01L29/41733 , H01L29/66742 , H01L29/78618
摘要： A semiconductor structure including a bottom source drain region arranged above front-end-of-line circuitry, a gate region disposed above and insulated from the bottom source drain region, a top source drain region disposed above and insulated from the gate region, and a channel region adjacent to the gate region and extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.
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