Invention Grant
- Patent Title: Bi-layer prepreg for reduced dielectric thickness
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Application No.: US15967122Application Date: 2018-04-30
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Publication No.: US11276618B2Publication Date: 2022-03-15
- Inventor: Jonathan Rosch , Andrew J. Brown
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP.
- Main IPC: H01L23/14
- IPC: H01L23/14 ; B32B27/12 ; B32B5/02 ; B32B5/26 ; B32B27/38 ; B32B27/36 ; H01L23/538 ; H01L21/48 ; H05K1/03 ; H01L23/498 ; H05K5/00 ; H01L23/00 ; H01L25/065

Abstract:
An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20190333832A1 BI-LAYER PREPREG FOR REDUCED DIELECTRIC THICKNESS Public/Granted day:2019-10-31
Information query
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