- 专利标题： Method of fabricating semiconductor device with reduced trench distortions
-
申请号： US17080248申请日： 2020-10-26
-
公开(公告)号： US11387113B2公开(公告)日： 2022-07-12
- 发明人: Yung-Sung Yen , Chung-Ju Lee , Chun-Kuang Chen , Chia-Tien Wu , Ta-Ching Yu , Kuei-Shun Chen , Ru-Gun Liu , Shau-Lin Shue , Tsai-Sheng Gau , Yung-Hsu Wu
- 申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Haynes and Boone, LLP
- 主分类号： H01L21/311
- IPC分类号： H01L21/311 ; H01L21/033 ; H01L21/3213 ; H01L21/768 ; H01L21/8234 ; H01L21/8238
摘要：
A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.