Invention Grant
- Patent Title: Metallic sealants in transistor arrangements
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Application No.: US15899590Application Date: 2018-02-20
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Publication No.: US11522059B2Publication Date: 2022-12-06
- Inventor: Abhishek A. Sharma , Tahir Ghani , Jack T. Kavalieros , Gilbert W. Dewey , Van H. Le , Lawrence D. Wong , Christopher J. Jezewski
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/786 ; H01L29/66 ; H01L29/423 ; H01L29/49 ; H01L29/78 ; H01L29/45 ; H01L23/29 ; H01L29/24 ; H01L29/22

Abstract:
Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.
Public/Granted literature
- US20190259844A1 METALLIC SEALANTS IN TRANSISTOR ARRANGEMENTS Public/Granted day:2019-08-22
Information query
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