Invention Grant
- Patent Title: Package architecture utilizing photoimageable dielectric (PID) for reduced bump pitch
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Application No.: US16473598Application Date: 2017-03-30
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Publication No.: US11574874B2Publication Date: 2023-02-07
- Inventor: Robert A. May , Sri Ranga Sai Boyapati , Kristof Darmawikarta , Hiroki Tanaka , Srinivas V. Pietambaram , Frank Truong , Praneeth Akkinepally , Andrew J. Brown , Lauren A. Link , Prithwish Chatterjee
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP.
- International Application: PCT/US2017/024995 WO 20170330
- International Announcement: WO2018/182610 WO 20181004
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48
Abstract:
An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.
Public/Granted literature
- US20210134727A1 PACKAGE ARCHITECTURE UTILIZING PHOTOIMAGEABLE DIELECTRIC (PID) FOR REDUCED BUMP PITCH Public/Granted day:2021-05-06
Information query
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