公开(公告)号：US11728265B2

公开(公告)日：2023-08-15

申请号：US16129711

申请日：2018-09-12

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian ,  Dilan Seneviratne ,  Yonggang Li ,  Sameer Paital ,  Darko Grujicic ,  Rengarajan Shanmugam ,  Melissa Wette ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00 ,  H01L27/01 ,  H01L23/64

CPC classification number: H01L23/5228 ,  H01L21/4846 ,  H01L21/76871 ,  H01L23/498 ,  H01L23/5226 ,  H01L23/647 ,  H01L24/09 ,  H01L27/016 ,  H01L28/24

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

公开(公告)号：US11728077B2

公开(公告)日：2023-08-15

申请号：US17482861

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498 ,  H01F17/00

CPC classification number: H01F1/20 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/2804 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01F2027/2809 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.

公开(公告)号：US11462432B2

公开(公告)日：2022-10-04

申请号：US15922749

申请日：2018-03-15

Applicant: Intel Corporation

Inventor： Frank Truong ,  Praneeth Akkinepally ,  Chelsea M. Groves ,  Whitney M. Bryks ,  Jason M. Gamba ,  Brandon C. Marin

IPC: B32B43/00 ,  H01L21/683 ,  H01L21/687 ,  C09J5/06 ,  H01L21/02

Abstract: A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.

公开(公告)号：US20220093515A1

公开(公告)日：2022-03-24

申请号：US17540079

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US20210305163A1

公开(公告)日：2021-09-30

申请号：US16832150

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US10546916B2

公开(公告)日：2020-01-28

申请号：US16024223

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20200006468A1

公开(公告)日：2020-01-02

申请号：US16024223

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC: H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20230345621A1

公开(公告)日：2023-10-26

申请号：US18344944

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC: H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/111 ,  H05K1/181

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.

公开(公告)号：US11233009B2

公开(公告)日：2022-01-25

申请号：US16832150

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US11158444B2

公开(公告)日：2021-10-26

申请号：US15894418

申请日：2018-02-12

Applicant: INTEL CORPORATION

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498 ,  H01F17/00

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.