公开(公告)号：US10410940B2

公开(公告)日：2019-09-10

申请号：US15639077

申请日：2017-06-30

申请人： Intel Corporation

发明人： Praneeth Akkinepally

IPC分类号： H01L23/48 ,  H01L23/13 ,  H01L23/522 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L25/16

摘要： An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material; forming a first layer, on the first dielectric material and the sacrificial material, which includes a first metal interconnect and a third dielectric material; decoupling the substrate from the first dielectric material and the sacrificial material; removing the sacrificial material to form an empty cavity with sidewalls comprising the first dielectric material; after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity; and forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis intersects the first and second dielectric materials and the first die. Other embodiments are described herein.

公开(公告)号：US11081448B2

公开(公告)日：2021-08-03

申请号：US16474019

申请日：2017-03-29

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC分类号： H01L23/538 ,  H01L23/52 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522

摘要： Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that, provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US10923443B2

公开(公告)日：2021-02-16

申请号：US16369708

申请日：2019-03-29

申请人： Intel Corporation

发明人： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC分类号： H01L23/495 ,  H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

摘要： A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US20190006252A1

公开(公告)日：2019-01-03

申请号：US15639077

申请日：2017-06-30

申请人： Intel Corporation

发明人： Praneeth Akkinepally

IPC分类号： H01L23/13 ,  H01L23/522 ,  H01L23/00 ,  H01L25/16

CPC分类号： H01L23/13 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/10 ,  H01L25/16 ,  H01L2224/16225

摘要： An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial material such that a horizontal axis intersects the first dielectric material and the sacrificial material; forming a first layer, on the first dielectric material and the sacrificial material, which includes a first metal interconnect and a third dielectric material; decoupling the substrate from the first dielectric material and the sacrificial material; removing the sacrificial material to form an empty cavity with sidewalls comprising the first dielectric material; after removing the sacrificial material to form the empty cavity, inserting a first die into the empty cavity; and forming a second dielectric material between the first dielectric material and the first die such that the horizontal axis intersects the first and second dielectric materials and the first die. Other embodiments are described herein.

公开(公告)号：US11652071B2

公开(公告)日：2023-05-16

申请号：US17158634

申请日：2021-01-26

申请人： Intel Corporation

发明人： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC分类号： H01L23/495 ,  H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

CPC分类号： H01L23/642 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L28/40

摘要： A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US11574874B2

公开(公告)日：2023-02-07

申请号：US16473598

申请日：2017-03-30

申请人： INTEL CORPORATION

发明人： Robert A. May ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Srinivas V. Pietambaram ,  Frank Truong ,  Praneeth Akkinepally ,  Andrew J. Brown ,  Lauren A. Link ,  Prithwish Chatterjee

IPC分类号： H01L23/538 ,  H01L21/48

摘要： An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US20190287841A1

公开(公告)日：2019-09-19

申请号：US15922749

申请日：2018-03-15

申请人： Intel Corporation

发明人： Frank Truong ,  Praneeth Akkinepally ,  Chelsea M. Groves ,  Whitney M. Bryks ,  Jason M. Gamba ,  Brandon C. Marin

IPC分类号： H01L21/683 ,  H01L21/687 ,  C09J5/06

摘要： A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.

公开(公告)号：US12087700B2

公开(公告)日：2024-09-10

申请号：US17391905

申请日：2021-08-02

申请人： Intel Corporation

发明人： Srinivas Venkata Ramanuja Pietambaram ,  Rahul N. Manepalli ,  Praneeth Akkinepally ,  Jesse C. Jones ,  Yosuke Kanaoka ,  Dilan Seneviratne

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0652 ,  H01L23/5221 ,  H01L23/5381 ,  H01L24/16 ,  H01L2224/023 ,  H01L2224/0233 ,  H01L2224/16235

摘要： Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：US11462432B2

公开(公告)日：2022-10-04

申请号：US15922749

申请日：2018-03-15

申请人： Intel Corporation

发明人： Frank Truong ,  Praneeth Akkinepally ,  Chelsea M. Groves ,  Whitney M. Bryks ,  Jason M. Gamba ,  Brandon C. Marin

IPC分类号： B32B43/00 ,  H01L21/683 ,  H01L21/687 ,  C09J5/06 ,  H01L21/02

摘要： A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.

公开(公告)号：US10985080B2

公开(公告)日：2021-04-20

申请号：US15778042

申请日：2015-11-24

申请人： Intel Corporation

发明人： Pramod Malatkar ,  Kyle Yazzie ,  Naga Sivakumar Yagnamurthy ,  Richard J. Harries ,  Dilan Seneviratne ,  Praneeth Akkinepally ,  Xuefei Wan ,  Yonggang Li ,  Robert L. Sankman

IPC分类号： H01L23/31 ,  H01L23/34 ,  H01L23/48 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

摘要： An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.