Invention Grant
- Patent Title: Testing through-silicon-vias
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Application No.: US17226216Application Date: 2021-04-09
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Publication No.: US11600349B2Publication Date: 2023-03-07
- Inventor: Thomas Vogelsang , William Ng , Frederick A. Ware
- Applicant: RAMBUS INC.
- Applicant Address: US CA San Jose
- Assignee: RAMBUS INC.
- Current Assignee: RAMBUS INC.
- Current Assignee Address: US CA San Jose
- Agency: Womble Bond Dickinson (US) LLP
- Main IPC: G11C29/02
- IPC: G11C29/02 ; H01L25/065 ; G01R31/28 ; G11C8/10 ; G11C5/02 ; H01L21/66 ; G11C29/04 ; G11C5/06

Abstract:
Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
Public/Granted literature
- US20210233599A1 TESTING THROUGH-SILICON-VIAS Public/Granted day:2021-07-29
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