- 专利标题： Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions
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申请号： US17023145申请日： 2020-09-16
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公开(公告)号： US11614770B2公开(公告)日： 2023-03-28
- 发明人: Jianhua Liu , Jinghui Zhu , Ning Song , Tianping Wang , Chienkuang Chen , Diwakar Chopperla , Tianxin Wang , Zhenyu Gu , Xiaozhi Lin
- 申请人： GOWIN Semiconductor Corporation
- 申请人地址： CN GuangZhou
- 专利权人： GOWIN Semiconductor Corporation
- 当前专利权人： GOWIN Semiconductor Corporation
- 当前专利权人地址： CN GuangZhou
- 代理机构： JW Law Group
- 代理商 James M. Wu
- 主分类号： G06F1/10
- IPC分类号： G06F1/10 ; G06F1/06 ; G06F30/396 ; G06F30/34 ; G06F1/08 ; G06F1/04
摘要：
A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.
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