公开(公告)号：US11216022B1

公开(公告)日：2022-01-04

申请号：US17023178

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/06

摘要： A field-programmable gate array (“FPGA”) contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals (“RCSs”) generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

公开(公告)号：US20210119632A1

公开(公告)日：2021-04-22

申请号：US16681376

申请日：2019-11-12

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Jiyong Zhang ,  Jianhua Liu

IPC分类号： H03K19/177 ,  G01R31/3185 ,  G01R31/302

摘要： A programmable semiconductor device contains a wireless communication block (“WCB”) capable of facilitating wirelessly field programmable gate array (“FPGA”) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (“CDB”) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (“LBs”) in FPGA in response to the configuration bitstream.

公开(公告)号：US20200177187A1

公开(公告)日：2020-06-04

申请号：US16741393

申请日：2020-01-13

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Jianhua Liu ,  Ning Song

IPC分类号： H03K19/17784 ,  H03K19/17724 ,  H03K19/17772

摘要： A process or method for facilitating configuring a field programmable gate array (“FPGA”) using a group of configurable logic blocks (“CLBs”) to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (“DPR”) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.

公开(公告)号：US11614770B2

公开(公告)日：2023-03-28

申请号：US17023145

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/10 ,  G06F1/06 ,  G06F30/396 ,  G06F30/34 ,  G06F1/08 ,  G06F1/04

摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

公开(公告)号：US20220083094A1

公开(公告)日：2022-03-17

申请号：US17023145

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/10

摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank 1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

公开(公告)号：US20210226633A1

公开(公告)日：2021-07-22

申请号：US17225001

申请日：2021-04-07

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Jiyong Zhang ,  Jianhua Liu

IPC分类号： H03K19/17758 ,  G01R31/3185 ,  G01R31/302 ,  H03K19/17728

摘要： A programmable semiconductor device contains a wireless communication block (“WCB”) capable of facilitating wirelessly field programmable gate array (“FPGA”) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (“CDB”) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (“LBs”) in FPGA in response to the configuration bitstream.

公开(公告)号：US10992298B1

公开(公告)日：2021-04-27

申请号：US16681376

申请日：2019-11-12

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Jiyong Zhang ,  Jianhua Liu

IPC分类号： H03K19/17758 ,  H03K19/17728 ,  G01R31/3185 ,  G01R31/302

摘要： A programmable semiconductor device contains a wireless communication block (“WCB”) capable of facilitating wirelessly field programmable gate array (“FPGA”) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (“CDB”) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (“LBs”) in FPGA in response to the configuration bitstream.

公开(公告)号：US10886925B2

公开(公告)日：2021-01-05

申请号：US16741393

申请日：2020-01-13

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Jianhua Liu ,  Ning Song

IPC分类号： H03K19/17784 ,  H03K19/17772 ,  H03K19/17724

摘要： A process or method for facilitating configuring a field programmable gate array (“FPGA”) using a group of configurable logic blocks (“CLBs”) to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (“DPR”) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.