公开(公告)号：US11157421B2

公开(公告)日：2021-10-26

申请号：US15857672

申请日：2017-12-29

申请人： Gowin Semiconductor Corporation

发明人： Jinghui Zhu ,  San-Ta Kow ,  Tun Jun Gao ,  Diwakar Chopperla ,  Chienkuang Chen ,  Ning Song

IPC分类号： G06F13/10 ,  H03K19/177 ,  G06F12/06 ,  G06F13/42 ,  G06F13/12

摘要： The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array. The present application solves the problem of the combination of a variety of different devices and the integration of processing capabilities with different applications.

公开(公告)号：US20190114268A1

公开(公告)日：2019-04-18

申请号：US15857672

申请日：2017-12-29

申请人： Gowin Semiconductor Corporation

发明人： Jinghui Zhu ,  San-Ta Kow ,  Tun Jun Gao ,  Diwakar Chopperla ,  Chienkuang Chen ,  Ning Song

IPC分类号： G06F13/10 ,  H03K19/177 ,  G06F13/42 ,  G06F12/06

摘要： The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array. The present application solves the problem of the combination of a variety of different devices and the integration of processing capabilities with different applications.

公开(公告)号：US11216022B1

公开(公告)日：2022-01-04

申请号：US17023178

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/06

摘要： A field-programmable gate array (“FPGA”) contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals (“RCSs”) generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

公开(公告)号：US20200177187A1

公开(公告)日：2020-06-04

申请号：US16741393

申请日：2020-01-13

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Jianhua Liu ,  Ning Song

IPC分类号： H03K19/17784 ,  H03K19/17724 ,  H03K19/17772

摘要： A process or method for facilitating configuring a field programmable gate array (“FPGA”) using a group of configurable logic blocks (“CLBs”) to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (“DPR”) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.

公开(公告)号：US11614770B2

公开(公告)日：2023-03-28

申请号：US17023145

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/10 ,  G06F1/06 ,  G06F30/396 ,  G06F30/34 ,  G06F1/08 ,  G06F1/04

摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

公开(公告)号：US20220083094A1

公开(公告)日：2022-03-17

申请号：US17023145

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/10

摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank 1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

公开(公告)号：US10886925B2

公开(公告)日：2021-01-05

申请号：US16741393

申请日：2020-01-13

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Jianhua Liu ,  Ning Song

IPC分类号： H03K19/17784 ,  H03K19/17772 ,  H03K19/17724

摘要： A process or method for facilitating configuring a field programmable gate array (“FPGA”) using a group of configurable logic blocks (“CLBs”) to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (“DPR”) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.