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    System level integrated circuit chip
    1.
    发明授权
    System level integrated circuit chip 有权

    公开(公告)号：US11157421B2

    公开(公告)日：2021-10-26

    申请号：US15857672

    申请日：2017-12-29

    申请人： Gowin Semiconductor Corporation

    发明人： Jinghui Zhu ,  San-Ta Kow ,  Tun Jun Gao ,  Diwakar Chopperla ,  Chienkuang Chen ,  Ning Song

    IPC分类号： G06F13/10 ,  H03K19/177 ,  G06F12/06 ,  G06F13/42 ,  G06F13/12

    摘要： The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array. The present application solves the problem of the combination of a variety of different devices and the integration of processing capabilities with different applications.

    SYSTEM LEVEL INTEGRATED CIRCUIT CHIP
    2.
    发明申请
    SYSTEM LEVEL INTEGRATED CIRCUIT CHIP 审中-公开

    公开(公告)号：US20190114268A1

    公开(公告)日：2019-04-18

    申请号：US15857672

    申请日：2017-12-29

    申请人： Gowin Semiconductor Corporation

    发明人： Jinghui Zhu ,  San-Ta Kow ,  Tun Jun Gao ,  Diwakar Chopperla ,  Chienkuang Chen ,  Ning Song

    IPC分类号： G06F13/10 ,  H03K19/177 ,  G06F13/42 ,  G06F12/06

    摘要： The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array. The present application solves the problem of the combination of a variety of different devices and the integration of processing capabilities with different applications.

    METHOD AND SYSTEM FOR PROVIDING REGIONAL ELECTRICAL GRID FOR POWER CONSERVATION IN A PROGRAMMABLE DEVICE
    5.
    发明申请
    METHOD AND SYSTEM FOR PROVIDING REGIONAL ELECTRICAL GRID FOR POWER CONSERVATION IN A PROGRAMMABLE DEVICE 审中-公开

    公开(公告)号：US20200177187A1

    公开(公告)日：2020-06-04

    申请号：US16741393

    申请日：2020-01-13

    申请人： GOWIN Semiconductor Corporation

    发明人： Jinghui Zhu ,  Jianhua Liu ,  Ning Song

    IPC分类号： H03K19/17784 ,  H03K19/17724 ,  H03K19/17772

    摘要： A process or method for facilitating configuring a field programmable gate array (“FPGA”) using a group of configurable logic blocks (“CLBs”) to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (“DPR”) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.

    Method and system for providing regional electrical grid for power conservation in a programmable device
    7.
    发明授权
    Method and system for providing regional electrical grid for power conservation in a programmable device 有权

    公开(公告)号：US10886925B2

    公开(公告)日：2021-01-05

    申请号：US16741393

    申请日：2020-01-13

    申请人： GOWIN Semiconductor Corporation

    发明人： Jinghui Zhu ,  Jianhua Liu ,  Ning Song

    IPC分类号： H03K19/17784 ,  H03K19/17772 ,  H03K19/17724

    摘要： A process or method for facilitating configuring a field programmable gate array (“FPGA”) using a group of configurable logic blocks (“CLBs”) to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (“DPR”) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.