公开(公告)号：US11614770B2

公开(公告)日：2023-03-28

申请号：US17023145

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/10 ,  G06F1/06 ,  G06F30/396 ,  G06F30/34 ,  G06F1/08 ,  G06F1/04

摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

公开(公告)号：US11216022B1

公开(公告)日：2022-01-04

申请号：US17023178

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/06

摘要： A field-programmable gate array (“FPGA”) contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals (“RCSs”) generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

公开(公告)号：US20220083094A1

公开(公告)日：2022-03-17

申请号：US17023145

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/10

摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank 1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.