公开(公告)号：US10521150B2

公开(公告)日：2019-12-31

申请号：US16028406

申请日：2018-07-05

申请人： Gowin Semiconductor Corporation

发明人： San-Ta Kow ,  Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F3/00 ,  G06F3/06

摘要： The present disclosure provides a data processing method and a device for a nonvolatile memory and a storage medium. The data processing method comprises: performing a full erase operation on the nonvolatile memory if a full erase operation command is received, such that the nonvolatile memory enters an initial state, wherein the initial state refers to a state in which all operations performed on the nonvolatile memory are valid; in the initial state, storing a data if the data is written in the memory is detected, wherein the data comprises a flag information; detecting the flag information if a data readout command triggered by a user is received; and identifying that the nonvolatile memory is in a default state and prohibiting the user from reading the data stored in the nonvolatile memory if the flag information is detected as an unreadable flag information.

公开(公告)号：US11614770B2

公开(公告)日：2023-03-28

申请号：US17023145

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/10 ,  G06F1/06 ,  G06F30/396 ,  G06F30/34 ,  G06F1/08 ,  G06F1/04

摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

公开(公告)号：US20220027071A1

公开(公告)日：2022-01-27

申请号：US16938771

申请日：2020-07-24

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F3/06 ,  G06F9/4401

摘要： A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.

公开(公告)号：US11216022B1

公开(公告)日：2022-01-04

申请号：US17023178

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/06

摘要： A field-programmable gate array (“FPGA”) contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals (“RCSs”) generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

公开(公告)号：US10997088B2

公开(公告)日：2021-05-04

申请号：US15633172

申请日：2017-06-26

申请人： Gowin Semiconductor Corporation, Ltd

发明人： San-Ta Kow ,  Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F21/00 ,  G06F12/14 ,  G06F3/06

摘要： A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.

公开(公告)号：US20180011803A1

公开(公告)日：2018-01-11

申请号：US15633172

申请日：2017-06-26

申请人： Gowin Semiconductor Corporation, Ltd

发明人： San-Ta Kow ,  Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F12/14 ,  G06F3/06

CPC分类号： G06F12/1408 ,  G06F3/0619 ,  G06F3/062 ,  G06F3/0623 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0688

摘要： A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.

公开(公告)号：US20230014412A1

公开(公告)日：2023-01-19

申请号：US17953317

申请日：2022-09-26

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F30/347

摘要： A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.

公开(公告)号：US20220083094A1

公开(公告)日：2022-03-17

申请号：US17023145

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/10

摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank 1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

公开(公告)号：US20190361624A1

公开(公告)日：2019-11-28

申请号：US16028406

申请日：2018-07-05

申请人： Gowin Semiconductor Corporation

发明人： San-Ta Kow ,  Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F3/06

摘要： The present disclosure provides a data processing method and a device for a nonvolatile memory and a storage medium. The data processing method comprises: performing a full erase operation on the nonvolatile memory if a full erase operation command is received, such that the nonvolatile memory enters an initial state, wherein the initial state refers to a state in which all operations performed on the nonvolatile memory are valid; in the initial state, storing a data if the data is written in the memory is detected, wherein the data comprises a flag information; detecting the flag information if a data readout command triggered by a user is received; and identifying that the nonvolatile memory is in a default state and prohibiting the user from reading the data stored in the nonvolatile memory if the flag information is detected as an unreadable flag information.

公开(公告)号：US11468220B2

公开(公告)日：2022-10-11

申请号：US16938798

申请日：2020-07-24

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F30/347

摘要： A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.