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公开(公告)号：US20230103119A1
公开(公告)日：2023-03-30
申请号：US17489749
申请日：2021-09-29
摘要： An automatic measuring system containing configurable integrated circuits is able to process information via captured images. The automatic measuring system includes a metering instrument, a camera, a recognition module, and a localization module. The metering instrument has at least one display for visually displaying a number and measures the amount of measurable substance or resources (i.e., electricity and water) consumed. The camera captures an image of the number representing at least a portion the amount of measurable substance. The recognition module is operable to generate a value in response to the image and the coordinates wherein the coordinates are used to decode the image via restoring captured image to the original readout counter value. The localization module is removably or remotely coupled to the camera and operable to generate the coordinates in accordance with the image captured by the camera.
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2.发明申请公开(公告)号：US20220393685A1
公开(公告)日：2022-12-08
申请号：US17891154
申请日：2022-08-19
发明人： Grant Thomas Jennings , Jinghui Zhu
IPC分类号： H03K19/17788 , H03K19/1776 , H03K19/17704 , H03K19/17784
摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
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3.发明授权公开(公告)号：US11496135B2
公开(公告)日：2022-11-08
申请号：US17325025
申请日：2021-05-19
发明人： Grant Thomas Jennings , Jinghui Zhu
IPC分类号： H03K19/177 , H03K19/17788 , H03K19/1776 , H03K19/17704 , H03K19/17784
摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
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4.发明授权公开(公告)号：US11216022B1
公开(公告)日：2022-01-04
申请号：US17023178
申请日：2020-09-16
发明人： Jianhua Liu , Jinghui Zhu , Ning Song , Tianping Wang , Chienkuang Chen , Diwakar Chopperla , Tianxin Wang , Zhenyu Gu , Xiaozhi Lin
IPC分类号： G06F1/06
摘要： A field-programmable gate array (“FPGA”) contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals (“RCSs”) generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.
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5.发明申请公开(公告)号：US20210305986A1
公开(公告)日：2021-09-30
申请号：US16836899
申请日：2020-03-31
发明人： Jinghui Zhu
IPC分类号： H03K19/17728 , H03K19/173
摘要： A programmable integrated circuit (“PIC”) device includes configurable logic blocks (“LBs”), routing connections, and configuration memory for performing user defined programmed logic functions. Each configurable LB, in one example, includes a set of lookup tables (“LUTs”) and associated registers. The LUTs, for example, are configured to generate one or more output signals in accordance with a set of input signals. The registers are arranged so that each register corresponds to one LUT. In one embodiment, a group of registers, instead of assigning to a group of LUTs across multiple configurable LBs, is allocated or configured as embedded signature registers in PSD. For example, a first register which corresponds or physically situated in the vicinity of first LUT can be designated as an embedded signature register for storing a fixed value or signature information for facilitating device or IC identification.
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公开(公告)号：US10997088B2
公开(公告)日：2021-05-04
申请号：US15633172
申请日：2017-06-26
发明人： San-Ta Kow , Jinghui Zhu , Diwakar Chopperla
摘要： A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.
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公开(公告)号：US20210119632A1
公开(公告)日：2021-04-22
申请号：US16681376
申请日：2019-11-12
发明人： Jinghui Zhu , Jiyong Zhang , Jianhua Liu
IPC分类号： H03K19/177 , G01R31/3185 , G01R31/302
摘要： A programmable semiconductor device contains a wireless communication block (“WCB”) capable of facilitating wirelessly field programmable gate array (“FPGA”) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (“CDB”) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (“LBs”) in FPGA in response to the configuration bitstream.
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8.发明申请公开(公告)号：US20200177187A1
公开(公告)日：2020-06-04
申请号：US16741393
申请日：2020-01-13
发明人： Jinghui Zhu , Jianhua Liu , Ning Song
IPC分类号： H03K19/17784 , H03K19/17724 , H03K19/17772
摘要： A process or method for facilitating configuring a field programmable gate array (“FPGA”) using a group of configurable logic blocks (“CLBs”) to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (“DPR”) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.
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公开(公告)号：US20180011803A1
公开(公告)日：2018-01-11
申请号：US15633172
申请日：2017-06-26
发明人： San-Ta Kow , Jinghui Zhu , Diwakar Chopperla
CPC分类号： G06F12/1408 , G06F3/0619 , G06F3/062 , G06F3/0623 , G06F3/0652 , G06F3/0679 , G06F3/0688
摘要： A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.
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10.发明授权公开(公告)号：US11614770B2
公开(公告)日：2023-03-28
申请号：US17023145
申请日：2020-09-16
发明人： Jianhua Liu , Jinghui Zhu , Ning Song , Tianping Wang , Chienkuang Chen , Diwakar Chopperla , Tianxin Wang , Zhenyu Gu , Xiaozhi Lin
摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.
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