- Patent Title: Voltage bin calibration based on a temporary voltage shift offset
-
Application No.: US17820792Application Date: 2022-08-18
-
Publication No.: US11823748B2Publication Date: 2023-11-21
- Inventor: Kishore Kumar Muchherla , Karl Schuh , Mustafa N Kaynak , Xiangang Luo , Shane Nowell , Devin Batutis , Sivagnanam Parthasarathy , Sampath Ratnam , Jiangang Wu , Peter Feeley
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/30 ; G11C16/10 ; G11C7/04 ; G11C16/32 ; G11C16/26

Abstract:
A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.
Public/Granted literature
- US20220392547A1 VOLTAGE BIN CALIBRATION BASED ON A TEMPORARY VOTLAGE SHIFT OFFSET Public/Granted day:2022-12-08
Information query