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公开(公告)号：US10824527B2
公开(公告)日：2020-11-03
申请号：US16504067
申请日：2019-07-05
Applicant: Micron Technology, Inc.
Inventor： Harish Reddy Singidi , Giuseppe Cariello , Deping He , Scott Anthony Stoller , Devin Batutis , Preston Allen Thomson
Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.
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公开(公告)号：US10096380B1
公开(公告)日：2018-10-09
申请号：US15692962
申请日：2017-08-31
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Scott Anthony Stoller , Preston Thomson , Devin Batutis , Harish Singidi , Kulachet Tanpairoj
Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.
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公开(公告)号：US11823748B2
公开(公告)日：2023-11-21
申请号：US17820792
申请日：2022-08-18
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Karl Schuh , Mustafa N Kaynak , Xiangang Luo , Shane Nowell , Devin Batutis , Sivagnanam Parthasarathy , Sampath Ratnam , Jiangang Wu , Peter Feeley
CPC classification number: G11C16/30 , G11C7/04 , G11C16/102 , G11C16/26 , G11C16/32 , G11C16/34 , G11C16/3427
Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.
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公开(公告)号：US20230195355A1
公开(公告)日：2023-06-22
申请号：US17733460
申请日：2022-04-29
Applicant: Micron Technology, Inc.
Inventor： Pitamber Shukla , Avinash Rajagiri , Devin Batutis
IPC: G06F3/06
CPC classification number: G06F3/0653 , G06F3/0616 , G06F3/0679
Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.
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公开(公告)号：US12106813B2
公开(公告)日：2024-10-01
申请号：US17733460
申请日：2022-04-29
Applicant: Micron Technology, Inc.
Inventor： Pitamber Shukla , Avinash Rajagiri , Devin Batutis
CPC classification number: G11C29/02 , G06F11/073 , G11C29/006 , G11C2029/0403
Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.
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Patent Agency Ranking
公开(公告)号：US20220392547A1
公开(公告)日：2022-12-08
申请号：US17820792
申请日：2022-08-18
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Karl Schuh , Mustafa N. Kaynak , Xiangang Luo , Shane Nowell , Devin Batutis , Sivagnanam Parthasarathy , Sampath Ratnam , Jiangang Wu , Peter Feeley
Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.
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公开(公告)号：US20190324876A1
公开(公告)日：2019-10-24
申请号：US16504067
申请日：2019-07-05
Applicant: Micron Technology, Inc.
Inventor： Harish Reddy Singidi , Giuseppe Cariello , Deping He , Scott Anthony Stoller , Devin Batutis , Preston Allen Thomson
Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.
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公开(公告)号：US10387281B2
公开(公告)日：2019-08-20
申请号：US15690903
申请日：2017-08-30
Applicant: Micron Technology, Inc.
Inventor： Harish Reddy Singidi , Giuseppe Cariello , Deping He , Scott Anthony Stoller , Devin Batutis , Preston Thomson
IPC: G06F11/20
Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.
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公开(公告)号：US10325670B2
公开(公告)日：2019-06-18
申请号：US16129422
申请日：2018-09-12
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Scott Anthony Stoller , Preston Thomson , Devin Batutis , Harish Reddy Singidi , Kulachet Tanpairoj
Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.
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公开(公告)号：US12124705B2
公开(公告)日：2024-10-22
申请号：US17848061
申请日：2022-06-23
Applicant: Micron Technology, Inc.
Inventor： Pitamber Shukla , Ching-Huang Lu , Devin Batutis
CPC classification number: G06F3/0619 , G06F3/0608 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F11/002 , G06F11/076
Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.
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