Invention Grant
- Patent Title: Integrated circuit device structures and double-sided electrical testing
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Application No.: US17112697Application Date: 2020-12-04
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Publication No.: US11854894B2Publication Date: 2023-12-26
- Inventor: Valluri R. Rao , Patrick Morrow , Rishabh Mehandru , Doug Ingerly , Kimin Jun , Kevin O'Brien , Paul Fischer , Szuya S. Liao , Bruce Block
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L21/822
- IPC: H01L21/822 ; H01L21/306 ; H01L21/683 ; H01L21/8238 ; H01L21/66 ; H01L23/528 ; H01L23/532 ; H01L23/00 ; H01L27/092 ; H01L27/12 ; H01L29/04 ; H01L29/06 ; H01L29/08 ; H01L29/16 ; H01L29/20 ; H01L29/66 ; G01R1/073 ; H01L25/065
Abstract:
Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
Public/Granted literature
- US20210175124A1 INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TESTING Public/Granted day:2021-06-10
Information query
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