- Patent Title: Device, a method used in forming a circuit structure, a method used in forming an array of elevationally-extending transistors and a circuit structure adjacent thereto
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Application No.: US17504313Application Date: 2021-10-18
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Publication No.: US11889695B2Publication Date: 2024-01-30
- Inventor: Paolo Tessariol , Justin B. Dorhout , Indra V. Chary , Jun Fang , Matthew Park , Zhiqiang Xie , Scott D. Stull , Daniel Osterberg , Jason Reece , Jian Li
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- The original application number of the division: US15705179 2017.09.14
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H10B43/27 ; H01L21/768 ; H01L21/311 ; H01L23/528 ; H01L21/02 ; H01L29/10 ; H01L23/522 ; H10B41/27 ; H10B43/50 ; H10B41/35 ; H10B43/10

Abstract:
A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.
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