Invention Grant
- Patent Title: Methods and apparatus to reduce read-modify-write cycles for non-aligned writes
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Application No.: US16882234Application Date: 2020-05-22
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Publication No.: US11940929B2Publication Date: 2024-03-26
- Inventor: Naveen Bhoria , Timothy David Anderson , Pete Michael Hippleheuser
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Brian D. Graham; Frank D. Cimino
- Main IPC: G06F12/0888
- IPC: G06F12/0888 ; G06F9/30 ; G06F9/54 ; G06F11/10 ; G06F12/02 ; G06F12/0802 ; G06F12/0804 ; G06F12/0806 ; G06F12/0811 ; G06F12/0815 ; G06F12/0817 ; G06F12/0853 ; G06F12/0855 ; G06F12/0864 ; G06F12/0884 ; G06F12/0891 ; G06F12/0895 ; G06F12/0897 ; G06F12/12 ; G06F12/121 ; G06F12/126 ; G06F12/127 ; G06F12/128 ; G06F13/16 ; G06F15/80 ; G11C5/06 ; G11C7/10 ; G11C7/22 ; G11C29/42 ; G11C29/44

Abstract:
Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.
Public/Granted literature
- US20200371946A1 METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-ALIGNED WRITES Public/Granted day:2020-11-26
Information query
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