- 专利标题: Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric
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申请号: US17080713申请日: 2020-10-26
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公开(公告)号: US11955532B2公开(公告)日: 2024-04-09
- 发明人: Jeffrey S. Leib , Jenny Hu , Anindya Dasgupta , Michael L. Hattendorf , Christopher P. Auth
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 分案原申请号: US15859356 2017.12.30
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L21/02 ; H01L21/033 ; H01L21/28 ; H01L21/285 ; H01L21/308 ; H01L21/311 ; H01L21/762 ; H01L21/768 ; H01L21/8234 ; H01L21/8238 ; H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L27/02 ; H01L27/088 ; H01L27/092 ; H01L29/06 ; H01L29/08 ; H01L29/165 ; H01L29/167 ; H01L29/417 ; H01L29/51 ; H01L29/78 ; H01L49/02 ; H10B10/00 ; H01L23/00
摘要:
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.
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