Invention Grant
- Patent Title: Semiconductor device
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Application No.: US18225186Application Date: 2023-07-24
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Publication No.: US12101945B2Publication Date: 2024-09-24
- Inventor: Tomoaki Atsumi , Shuhei Nagatsuka , Tamae Moriwaka , Yuta Endo
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi
- Agency: Fish & Richardson P.C.
- Priority: JP 14045406 2014.03.07
- Main IPC: H10B69/00
- IPC: H10B69/00 ; G11C7/16 ; G11C8/14 ; G11C11/24 ; G11C11/403 ; G11C11/408 ; H01L27/06 ; H01L29/24 ; H01L29/786 ; H10B41/20 ; H10B41/70

Abstract:
[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.
Public/Granted literature
- US20230371286A1 SEMICONDUCTOR DEVICE Public/Granted day:2023-11-16
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