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公开(公告)号：US20240179900A1
公开(公告)日：2024-05-30
申请号：US18086668
申请日：2022-12-22
发明人： Hsiao-Hua Lu , Yung-Tien Peng , Chun-Hao Huang
CPC分类号： H01L27/1156 , H01L27/11519 , H01L27/11524
摘要： A non-volatile memory cell includes a tunneling part; a coupling transistor, including a coupling gate part, a first conductive region and a second conductive region, wherein the coupling gate part is coupled to the tunneling part and disposed in the first conductive region; a read transistor with a read gate part coupled to the tunneling part for forming an electron tunneling ejection path in an erase mode, and forming an electron tunneling injection path in a program mode; and a select transistor, connected in series with the read transistor, for forming a read path with the read transistor in a read mode.
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2.发明授权公开(公告)号：US11980029B2
公开(公告)日：2024-05-07
申请号：US17883652
申请日：2022-08-09
发明人： Hsueh-Wei Chen
摘要： An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.
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公开(公告)号：US20240120339A1
公开(公告)日：2024-04-11
申请号：US18537929
申请日：2023-12-13
发明人： Shunpei YAMAZAKI
IPC分类号： H01L27/105 , G11C11/405 , G11C16/04 , H01L21/02 , H01L21/46 , H01L21/8258 , H01L27/12 , H01L29/06 , H01L29/786 , H10B41/10 , H10B41/20 , H10B41/30 , H10B41/35 , H10B41/70
CPC分类号： H01L27/105 , G11C11/405 , G11C16/0433 , H01L21/02664 , H01L21/46 , H01L21/8258 , H01L27/1225 , H01L29/06 , H01L29/7869 , H01L29/78693 , H10B41/10 , H10B41/20 , H10B41/30 , H10B41/35 , H10B41/70 , H01L27/0207
摘要： Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
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公开(公告)号：US20230397447A1
公开(公告)日：2023-12-07
申请号：US18235995
申请日：2023-08-21
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO
IPC分类号： H10B99/00 , H01L27/12 , H01L29/24 , H01L29/16 , G11C11/405 , G11C16/04 , H01L27/105 , H01L27/118 , H10B41/20 , H10B41/70 , H10B69/00 , H01L29/786
CPC分类号： H10B99/00 , H01L27/1207 , H01L29/24 , H01L29/16 , G11C11/405 , G11C16/0433 , H01L27/105 , H01L27/11803 , H01L27/1225 , H10B41/20 , H10B41/70 , H10B69/00 , H01L29/7869 , H01L27/124 , H01L27/1255 , H01L29/247 , H01L29/78693 , H01L29/78696 , G11C2211/4016 , H01L21/8221
摘要： An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
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公开(公告)号：US20230371286A1
公开(公告)日：2023-11-16
申请号：US18225186
申请日：2023-07-24
发明人： Tomoaki ATSUMI , Shuhei NAGATSUKA , Tamae MORIWAKA , Yuta ENDO
IPC分类号： H10B69/00 , H01L29/786 , H01L27/06 , G11C7/16 , G11C8/14 , G11C11/403 , G11C11/408 , H10B41/20 , H10B41/70 , G11C11/24 , H01L29/24
CPC分类号： H10B69/00 , H01L29/7869 , H01L27/0688 , G11C7/16 , G11C8/14 , G11C11/403 , G11C11/4085 , H10B41/20 , H10B41/70 , G11C11/24 , H01L29/24
摘要： [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.-
公开(公告)号：US11737279B2
公开(公告)日：2023-08-22
申请号：US17835134
申请日：2022-06-08
申请人： KIOXIA CORPORATION
发明人： Go Oike
IPC分类号： H01L27/11573 , H10B43/40 , H01L23/528 , H01L23/522 , H01L27/06 , H10B41/20 , H10B41/23 , H10B41/27 , H10B41/30 , H10B41/70 , H10B43/20 , H10B43/27 , H10B43/35 , H10B53/20 , H01L23/532
CPC分类号： H10B43/40 , H01L23/528 , H01L23/5226 , H01L27/0688 , H10B41/20 , H10B41/23 , H10B41/27 , H10B41/30 , H10B41/70 , H10B43/20 , H10B43/27 , H10B43/35 , H10B53/20 , H01L23/53228 , H01L23/53257 , H01L23/53271
摘要： A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.
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公开(公告)号：US20240257874A1
公开(公告)日：2024-08-01
申请号：US18103350
申请日：2023-01-30
摘要： A memory device includes a first well region, a second well region, and third well regions. The second well region is interposed between the first region and the third well regions, and the third well regions are separated from one another. The memory device includes floating gates disposed over the first to third well regions, wherein each of the floating gates continuously extends from the first well region to a corresponding one of the third well regions. The memory device includes a bit line write region disposed within the second well region. The bit line write region comprises first source/drain regions on opposite sides of each floating gate. The memory device includes a bit line read region disposed within the second well region and spaced from the bit line write region. The bit line read region comprises second source/drain regions on the opposite sides of each floating gate.
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公开(公告)号：US12020749B2
公开(公告)日：2024-06-25
申请号：US17530676
申请日：2021-11-19
发明人： Daniele Vimercati
CPC分类号： G11C16/045 , G11C16/10 , G11C16/26 , H10B41/70
摘要： The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.
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公开(公告)号：US20240136358A1
公开(公告)日：2024-04-25
申请号：US18538009
申请日：2023-12-13
发明人： Shunpei YAMAZAKI
IPC分类号： H01L27/105 , G11C11/405 , G11C16/04 , H01L21/02 , H01L21/46 , H01L21/8258 , H01L27/12 , H01L29/06 , H01L29/786 , H10B41/10 , H10B41/20 , H10B41/30 , H10B41/35 , H10B41/70
CPC分类号： H01L27/105 , G11C11/405 , G11C16/0433 , H01L21/02664 , H01L21/46 , H01L21/8258 , H01L27/1225 , H01L29/06 , H01L29/7869 , H01L29/78693 , H10B41/10 , H10B41/20 , H10B41/30 , H10B41/35 , H10B41/70 , H01L27/0207
摘要： Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
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公开(公告)号：US20240008280A1
公开(公告)日：2024-01-04
申请号：US18346473
申请日：2023-07-03
申请人： Kioxia Corporation
发明人： Go OIKE
IPC分类号： H10B43/40 , H01L23/528 , H01L23/522 , H01L27/06 , H10B41/20 , H10B41/23 , H10B41/27 , H10B41/30 , H10B41/70 , H10B43/20 , H10B43/27 , H10B43/35 , H10B53/20
CPC分类号： H10B43/40 , H01L23/528 , H01L23/5226 , H01L27/0688 , H10B41/20 , H10B41/23 , H10B41/27 , H10B41/30 , H10B41/70 , H10B43/20 , H10B43/27 , H10B43/35 , H10B53/20 , H01L23/53228
摘要： A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.
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