Invention Grant
- Patent Title: System and method for parallel memory test
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Application No.: US18453400Application Date: 2023-08-22
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Publication No.: US12142337B2Publication Date: 2024-11-12
- Inventor: Nitesh Mishra , Nikita Naresh
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Michael T. Gabrik; Frank D. Cimino
- Priority: IN202141018707 20210423
- Main IPC: G11C29/46
- IPC: G11C29/46 ; G11C29/12 ; G11C29/18 ; G11C29/38 ; H03K19/173

Abstract:
A device including a controller coupled to memory components via a forward data path, and a signature register coupled to the memory components via a backward data path. The controller provides memory address signals and a controller clock signal to the memory components via the forward data path, which includes first circuitry to provide test-enable signals to the memory components that enable the memory components to read stored memory values. The backward data path includes second circuitry to receive from the memory components a set of memory signals and combine them into a combined signal. Each memory signal is associated with a respective one of the memory components and includes at least one stored memory value read from the corresponding memory component. The signature register calculates a test signature based on the combined signal and compares the test signature to an expected signature.
Public/Granted literature
- US20230402124A1 SYSTEM AND METHOD FOR PARALLEL MEMORY TEST Public/Granted day:2023-12-14
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