-
公开(公告)号：US11680984B1
公开(公告)日：2023-06-20
申请号：US17683126
申请日：2022-02-28
发明人： Wilson Pradeep , Aravinda Acharya , Nikita Naresh
IPC分类号： G01R31/3185 , G01R31/317 , G01R31/319 , G01R31/3177
CPC分类号： G01R31/318536 , G01R31/3177 , G01R31/31727 , G01R31/31926
摘要： In some examples, a circuit includes a custom control data register (CCDR) circuit having a scan path. The CCDR circuit includes a shift register and an update register. The shift register is configured to receive scan data from a scan data input (CDR_SCAN_IN) on a first clock edge responsive to a scan enable signal (CDR_SCAN_EN) being enabled. The update register is configured to receive data from the shift register on a second clock edge after the first clock edge when the scan enable (CDR_SCAN_EN) is enabled. The update register data is asserted as a scan data output (CDR_SCAN_OUT). The second scan path includes the scan data input, the shift register, the update register, and the scan data output.
-
公开(公告)号：US20230152373A1
公开(公告)日：2023-05-18
申请号：US18155190
申请日：2023-01-17
发明人： Prakash Narayanan , Nikita Naresh
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31724 , G01R31/31703
摘要： A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.
-
公开(公告)号：US20170157524A1
公开(公告)日：2017-06-08
申请号：US15434717
申请日：2017-02-16
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C29/38 , G11C29/40 , G11C2029/0401 , G11C2029/2602
摘要： A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
-
公开(公告)号：US11776656B2
公开(公告)日：2023-10-03
申请号：US17538982
申请日：2021-11-30
发明人： Nitesh Mishra , Nikita Naresh
IPC分类号： G11C29/18 , G11C29/46 , G11C29/38 , H03K19/173 , G11C29/12
CPC分类号： G11C29/46 , G11C29/12015 , G11C29/18 , G11C29/38 , H03K19/1737
摘要： An apparatus includes a controller adapted to be coupled to memory components in parallel and configured to provide memory address signals and a controller clock signal to the memory components, a memory enable logic circuit coupled to the controller and adapted to be coupled to the memory components in parallel and configured to provide test-enable signals to the memory components. The test-enable signals enable, with the controller clock signal, the memory components to read locally stored memory values. The apparatus includes a multiplexer adapted to be coupled to the memory components in parallel and configured to receive from the memory components memory signals that include the memory values in respective sequences of the memory clock signals, and a pipeline coupled to the multiplexer and the controller and configured to receive the memory values from the multiplexer and send the memory values to a multiple input signature register of the controller.
-
公开(公告)号：US20220358230A1
公开(公告)日：2022-11-10
申请号：US17354777
申请日：2021-06-22
发明人： Prakash Narayanan , Nikita Naresh
摘要： Methods and apparatus are disclosed to protect secure assets using scan operations. One example apparatus includes logic circuitry including a scan chain that includes data storage elements and design logic coupled to the scan chain. The example apparatus also includes data storage to store secure data. The design logic is coupled to the data storage. The example apparatus also includes a security controller to transition the apparatus out of a secure mode of operation. The transition includes the security controller to cause the scan chain to serially shift secure scan data from an input of the scan chain into each data storage element of the data storage elements of the scan chain.
-
公开(公告)号：US20170125125A1
公开(公告)日：2017-05-04
申请号：US15066924
申请日：2016-03-10
IPC分类号： G11C29/12
CPC分类号： G11C29/12 , G11C29/38 , G11C29/40 , G11C2029/0401 , G11C2029/2602
摘要： A built-in self-test (BIST) parallel memory test architecture for an integrated circuit of the system-on-a-chip (SoC) type. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
-
公开(公告)号：US10818374B2
公开(公告)日：2020-10-27
申请号：US16271660
申请日：2019-02-08
发明人： Prakash Narayanan , Nikita Naresh , Prathyusha Teja Inuganti , Rakesh Channabasappa Yaraduyathinahalli , Aravinda Acharya , Jasbir Singh , Naveen Ambalametil Narayanan
IPC分类号： G11C29/38 , G11C17/00 , G11C29/00 , G11C11/00 , G11C29/10 , G11C29/12 , G11C29/04 , G11C29/08 , G11C14/00 , G06F12/06 , G06F9/4401
摘要： A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.
-
公开(公告)号：US20180174663A1
公开(公告)日：2018-06-21
申请号：US15896817
申请日：2018-02-14
IPC分类号： G11C29/12
CPC分类号： G11C29/12 , G11C29/38 , G11C29/40 , G11C2029/0401 , G11C2029/2602
摘要： A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
-
公开(公告)号：US09899103B2
公开(公告)日：2018-02-20
申请号：US15434717
申请日：2017-02-16
CPC分类号： G11C29/12 , G11C29/38 , G11C29/40 , G11C2029/0401 , G11C2029/2602
摘要： A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
-
公开(公告)号：US11852683B2
公开(公告)日：2023-12-26
申请号：US18155190
申请日：2023-01-17
发明人： Prakash Narayanan , Nikita Naresh
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/31724
摘要： A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.013 秒)
