Invention Grant
- Patent Title: Stacked structure for CMOS image sensors including through-substrate-via contacting negative bias circuit
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Application No.: US17336852Application Date: 2021-06-02
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Publication No.: US12176370B2Publication Date: 2024-12-24
- Inventor: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Wen-Chang Kuo , Sheng-Chau Chen , Feng-Chi Hung , Sheng-Chan Li
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L27/146
- IPC: H01L27/146

Abstract:
Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.
Public/Granted literature
- US20220238568A1 STACKED STRUCTURE FOR CMOS IMAGE SENSORS Public/Granted day:2022-07-28
Information query
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