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    Method of forming semiconductor device with gate
    2.
    发明授权
    Method of forming semiconductor device with gate 有权

    公开(公告)号：US11600727B2

    公开(公告)日：2023-03-07

    申请号：US16892458

    申请日：2020-06-04

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jung-Chi Jeng ,  I-Chih Chen ,  Wen-Chang Kuo ,  Ying-Hao Chen ,  Ru-Shang Hsiao ,  Chih-Mu Huang

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

    Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.

    Stacked structure for CMOS image sensors including through-substrate-via contacting negative bias circuit
    3.
    发明授权
    Stacked structure for CMOS image sensors including through-substrate-via contacting negative bias circuit 有权

    公开(公告)号：US12176370B2

    公开(公告)日：2024-12-24

    申请号：US17336852

    申请日：2021-06-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Sheng-Chau Chen ,  Feng-Chi Hung ,  Sheng-Chan Li

    IPC: H01L27/146

    Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20150200299A1

    公开(公告)日：2015-07-16

    申请号：US14224961

    申请日：2014-03-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： I-Chih CHEN ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167

    CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

    Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

    Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括衬底; 在衬底中具有第一掺杂剂的源/漏区; 阻挡层，其具有形成在衬底中的源极/漏极区周围的第二掺杂物。 当半导体器件按比例缩小时，源极/漏极区域中的掺杂分布可能影响阈值电压均匀性，所提供的半导体器件可以通过阻挡层来改善阈值电压均匀性以控制掺杂分布。

    Method of forming semiconductor device with gate
    7.
    发明授权
    Method of forming semiconductor device with gate 有权

    公开(公告)号：US10680103B2

    公开(公告)日：2020-06-09

    申请号：US15670978

    申请日：2017-08-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jung-Chi Jeng ,  I-Chih Chen ,  Wen-Chang Kuo ,  Ying-Hao Chen ,  Ru-Shang Hsiao ,  Chih-Mu Huang

    IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

    Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate, and the isolation structure surrounds an active region of the semiconductor substrate. The method also includes forming a gate over the semiconductor substrate, and the gate is across the active region and extends onto the isolation structure. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, the end portions are over the isolation structure. The method includes forming a support film over the isolation structure, and the support film is a continuous film which continuously covers the isolation structure and at least one end portion of the gate.

    STACKED STRUCTURE FOR CMOS IMAGE SENSORS
    9.
    发明申请
    STACKED STRUCTURE FOR CMOS IMAGE SENSORS 有权

    公开(公告)号：US20220238568A1

    公开(公告)日：2022-07-28

    申请号：US17336852

    申请日：2021-06-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Sheng-Chau Chen ,  Feng-Chi Hung ,  Sheng-Chan Li

    IPC: H01L27/146

    Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

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