Invention Grant
- Patent Title: Gate-all-around transistor with reduced source/drain contact resistance
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Application No.: US17335502Application Date: 2021-06-01
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Publication No.: US12191151B2Publication Date: 2025-01-07
- Inventor: Jui-Ping Lin , Chen-Ming Lee , Fu-Kai Yang , Mei-Yun Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/285
- IPC: H01L21/285 ; H01L21/02 ; H01L21/3065 ; H01L21/311 ; H01L21/768 ; H01L21/8234 ; H01L29/06 ; H01L29/08 ; H01L29/40 ; H01L29/417 ; H01L29/423 ; H01L29/45 ; H01L29/66 ; H01L29/786

Abstract:
A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.
Public/Granted literature
- US20220310398A1 Contact Resistance Reduction for Transistors Public/Granted day:2022-09-29
Information query
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