发明申请
- 专利标题： Method of fabricating a semiconductor device with a trench isolation structure and semiconductor device
- 专利标题（中）： 制造具有沟槽隔离结构和半导体器件的半导体器件的方法
-
申请号： US11033322申请日： 2005-01-12
-
公开(公告)号： US20050124107A1公开(公告)日： 2005-06-09
- 发明人: Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
- 申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 优先权： JP2001-245209 20010813
- 主分类号： H01L21/8247
- IPC分类号： H01L21/8247 ; H01L21/76 ; H01L21/762 ; H01L21/8242 ; H01L27/108 ; H01L27/115 ; H01L29/788 ; H01L29/792 ; H01L21/8238 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119
摘要：
The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
公开/授权文献
信息查询
