发明申请
- 专利标题: Fabrication method of wafer level chip scale packages
- 专利标题(中): 晶圆级芯片级封装的制作方法
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申请号: US11145994申请日: 2005-06-07
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公开(公告)号: US20050277293A1公开(公告)日: 2005-12-15
- 发明人: Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
- 申请人: Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
- 优先权: KR2004-44050 20040615
- 主分类号: H01L23/28
- IPC分类号: H01L23/28 ; C25D5/02 ; C25D7/12 ; H01L21/288 ; H01L21/48 ; H01L21/60 ; H01L21/768 ; H01L23/31 ; H01L23/48
摘要:
A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.
公开/授权文献
- US07524763B2 Fabrication method of wafer level chip scale packages 公开/授权日:2009-04-28