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公开(公告)号：US20050277293A1
公开(公告)日：2005-12-15
申请号：US11145994
申请日：2005-06-07
申请人： Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
发明人： Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
IPC分类号： H01L23/28 , C25D5/02 , C25D7/12 , H01L21/288 , H01L21/48 , H01L21/60 , H01L21/768 , H01L23/31 , H01L23/48
CPC分类号： C25D7/12 , C25D5/02 , H01L21/2885 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.
摘要翻译： 制造晶片级芯片级封装的方法可包括形成穿透IC芯片的芯片焊盘的孔。 基底金属层可以形成在晶片的第一面上以覆盖孔的内表面。 电极金属层可以填充孔并在芯片垫上升起。 可以研磨晶片的第二面，使得孔中的电极金属层可以通过第二面露出。 通过电镀，可以在通过第二面暴露的电极金属层上形成电镀凸块。 可以选择性地去除贱金属层以隔离相邻的电极金属层。 可以沿着划线锯切晶片以将单独的封装与晶片分开。
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公开(公告)号：US07524763B2
公开(公告)日：2009-04-28
申请号：US11145994
申请日：2005-06-07
申请人： Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
发明人： Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
IPC分类号： H01L21/44
CPC分类号： C25D7/12 , C25D5/02 , H01L21/2885 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.
摘要翻译： 制造晶片级芯片级封装的方法可包括形成穿透IC芯片的芯片焊盘的孔。 基底金属层可以形成在晶片的第一面上以覆盖孔的内表面。 电极金属层可以填充孔并在芯片垫上升起。 可以研磨晶片的第二面，使得孔中的电极金属层可以通过第二面露出。 通过电镀，可以在通过第二面暴露的电极金属层上形成电镀凸块。 可以选择性地去除贱金属层以隔离相邻的电极金属层。 可以沿着划线锯切晶片以将单独的封装与晶片分开。
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公开(公告)号：US07151009B2
公开(公告)日：2006-12-19
申请号：US11038210
申请日：2005-01-21
申请人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-min Sim
发明人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-min Sim
CPC分类号： H01L21/563 , H01L23/3114 , H01L23/3128 , H01L23/481 , H01L24/29 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83194 , H01L2225/06513 , H01L2225/06541 , H01L2225/06582 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： Provided is a method for manufacturing WLCSP devices that includes preparing at least two wafers, each wafer having a plurality of corresponding semiconductor chips, each semiconductor chip having through electrodes formed in the peripheral surface region, forming or applying a solid adhesive region to a central surface region, stacking a plurality of wafers and attaching corresponding chips provided on adjacent wafers with the solid adhesive region and connecting corresponding through electrodes of adjacent semiconductor chips, dividing the stacked wafers into individual chip stack packages, and injecting a liquid adhesive into a space remaining between adjacent semiconductor chips incorporated in the resulting chip stack package. By reducing the likelihood of void regions between adjacent semiconductor chips, it is expected that a method according to the exemplary embodiments of the present invention exhibit improved mechanical stability and reliability.
摘要翻译： 提供了一种制造WLCSP器件的方法，其包括制备至少两个晶片，每个晶片具有多个对应的半导体芯片，每个半导体芯片具有形成在外围表面区域中的通孔，形成或施加固体粘合剂区域到中心表面 区域，堆叠多个晶片，并将设置在相邻晶片上的相应芯片与固体粘合剂区域连接并且通过相邻半导体芯片的电极相对应地连接，将堆叠的晶片分成单独的芯片堆叠封装，并将液体粘合剂注入到 相邻的半导体芯片结合在所得的芯片堆叠封装中。 通过降低相邻半导体芯片之间的空隙区域的可能性，预期根据本发明的示例性实施例的方法表现出改进的机械稳定性和可靠性。
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公开(公告)号：US20050280160A1
公开(公告)日：2005-12-22
申请号：US11038210
申请日：2005-01-21
申请人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
发明人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
CPC分类号： H01L21/563 , H01L23/3114 , H01L23/3128 , H01L23/481 , H01L24/29 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83194 , H01L2225/06513 , H01L2225/06541 , H01L2225/06582 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： Provided is a method for manufacturing WLCSP devices that includes preparing at least two wafers, each wafer having a plurality of corresponding semiconductor chips, each semiconductor chip having through electrodes formed in the peripheral surface region, forming or applying a solid adhesive region to a central surface region, stacking a plurality of wafers and attaching corresponding chips provided on adjacent wafers with the solid adhesive region and connecting corresponding through electrodes of adjacent semiconductor chips, dividing the stacked wafers into individual chip stack packages, and injecting a liquid adhesive into a space remaining between adjacent semiconductor chips incorporated in the resulting chip stack package. By reducing the likelihood of void regions between adjacent semiconductor chips, it is expected that a method according to the exemplary embodiments of the present invention exhibit improved mechanical stability and reliability.
摘要翻译： 提供了一种制造WLCSP器件的方法，其包括制备至少两个晶片，每个晶片具有多个对应的半导体芯片，每个半导体芯片具有形成在外围表面区域中的通孔，形成或施加固体粘合剂区域到中心表面 区域，堆叠多个晶片，并将设置在相邻晶片上的相应芯片与固体粘合剂区域连接并且通过相邻半导体芯片的电极相对应地连接，将堆叠的晶片分成单独的芯片堆叠封装，并将液体粘合剂注入到 相邻的半导体芯片结合在所得的芯片堆叠封装中。 通过降低相邻半导体芯片之间的空隙区域的可能性，预期根据本发明的示例性实施例的方法表现出改进的机械稳定性和可靠性。
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公开(公告)号：US20070200216A1
公开(公告)日：2007-08-30
申请号：US11703900
申请日：2006-12-19
申请人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
发明人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
IPC分类号： H01L23/02
CPC分类号： H01L21/563 , H01L23/3114 , H01L23/3128 , H01L23/481 , H01L24/29 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83194 , H01L2225/06513 , H01L2225/06541 , H01L2225/06582 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： Provided is a chip stack package that may include a lower semiconductor chip, an upper semiconductor chip stacked on the lower semiconductor chip, and at least one adhesive formed in space between the lower semiconductor chip and the upper semiconductor chip. The at least one adhesive may include a first adhesive and a second adhesive. The first adhesive may be formed in a portion of the space, and the second adhesive may be formed in the space except for a region in which the first adhesive is provided. The space between adjacent semiconductor chips may be completely filled with the at least one adhesive. Therefore, a chip stack package according to the exemplary embodiments of the present invention may exhibit improved mechanical stability and reliability.
摘要翻译： 提供了一种芯片堆叠封装，其可以包括下半导体芯片，堆叠在下半导体芯片上的上半导体芯片，以及形成在下半导体芯片和上半导体芯片之间的空间中的至少一个粘合剂。 所述至少一种粘合剂可以包括第一粘合剂和第二粘合剂。 第一粘合剂可以形成在空间的一部分中，并且第二粘合剂可以形成在除了设置第一粘合剂的区域之外的空间中。 相邻的半导体芯片之间的空间可以被至少一个粘合剂完全填充。 因此，根据本发明的示例性实施例的芯片堆叠封装可以表现出改进的机械稳定性和可靠性。
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公开(公告)号：US07786594B2
公开(公告)日：2010-08-31
申请号：US11822630
申请日：2007-07-09
申请人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
发明人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.
摘要翻译： 一种晶片级堆叠结构，包括包括第一芯片尺寸的至少一个第一器件芯片的第一晶片，其中每个第一器件芯片包含第一多个输入/输出（I / O）焊盘，第二晶片包括至少一个 第二芯片尺寸小于第一芯片尺寸的第二器件芯片，其中每个第二器件芯片包含第二多个I / O焊盘，其中所述至少一个第二器件芯片增加到所述第一芯片尺寸，其中所述第一晶片 并且第二晶片被堆叠，并且其中第一晶片和第二晶片彼此耦合。 一种系统级封装，包括晶片级堆叠结构，其包括具有第一多个输入/输出（I / O）焊盘的至少一个第一器件芯片和至少一个具有第二多个I / O焊盘的第二器件芯片 ，以及与晶片级堆叠结构连接的公共电路板。
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公开(公告)号：US20070170576A1
公开(公告)日：2007-07-26
申请号：US11727760
申请日：2007-03-28
申请人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
发明人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
IPC分类号： H01L23/02
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.
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公开(公告)号：US20100320597A1
公开(公告)日：2010-12-23
申请号：US12805321
申请日：2010-07-26
申请人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
发明人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
IPC分类号： H01L23/48
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system-in-package, comprising a wafer level stack structure, including at least one first device chip including a first device region having a plurality of input/output(I/O) pads, and at least one second device chip including a second device region having a plurality of input/output(I/O) pads and a second peripheral region surrounding the second device region, wherein the size of the second device region is different from the size of the first device region, wherein the at least one first device chip and the at least one second device chip have approximately equal size; and a common circuit board to which the wafer level stack structure is connected.
摘要翻译： 一种系统级封装，包括晶片级堆叠结构，其包括至少一个包括具有多个输入/输出（I / O）焊盘的第一器件区域的第一器件芯片，以及包括第二器件芯片的至少一个第二器件芯片 器件区域具有多个输入/输出（I / O）焊盘和围绕第二器件区域的第二外围区域，其中第二器件区域的尺寸不同于第一器件区域的尺寸，其中至少一个 第一器件芯片和至少一个第二器件芯片具有大致相等的尺寸; 以及连接晶片级堆叠结构的公共电路板。
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公开(公告)号：US08278766B2
公开(公告)日：2012-10-02
申请号：US12805321
申请日：2010-07-26
申请人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
发明人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system-in-package, comprising a wafer level stack structure, including at least one first device chip including a first device region having a plurality of input/output(I/O) pads, and at least one second device chip including a second device region having a plurality of input/output(I/O) pads and a second peripheral region surrounding the second device region, wherein the size of the second device region is different from the size of the first device region, wherein the at least one first device chip and the at least one second device chip have approximately equal size; and a common circuit board to which the wafer level stack structure is connected.
摘要翻译： 一种系统级封装，包括晶片级堆叠结构，其包括至少一个包括具有多个输入/输出（I / O）焊盘的第一器件区域的第一器件芯片，以及包括第二器件芯片的至少一个第二器件芯片 器件区域具有多个输入/输出（I / O）焊盘和围绕第二器件区域的第二外围区域，其中第二器件区域的尺寸不同于第一器件区域的尺寸，其中至少一个 第一器件芯片和至少一个第二器件芯片具有大致相等的尺寸; 以及连接晶片级堆叠结构的公共电路板。
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公开(公告)号：US20070257350A1
公开(公告)日：2007-11-08
申请号：US11822630
申请日：2007-07-09
申请人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
发明人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
IPC分类号： H01L23/02
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.
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