公开(公告)号：US20050277293A1

公开(公告)日：2005-12-15

申请号：US11145994

申请日：2005-06-07

申请人： Soon-Bum Kim ,  Ung-Kwang Kim ,  Keum-Hee Ma ,  Young-Hee Song ,  Sung-Min Sim ,  Se-Yong Oh ,  Kang-Wook Lee ,  Se-Young Jeong

发明人： Soon-Bum Kim ,  Ung-Kwang Kim ,  Keum-Hee Ma ,  Young-Hee Song ,  Sung-Min Sim ,  Se-Yong Oh ,  Kang-Wook Lee ,  Se-Young Jeong

IPC分类号： H01L23/28 ,  C25D5/02 ,  C25D7/12 ,  H01L21/288 ,  H01L21/48 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48

CPC分类号： C25D7/12 ,  C25D5/02 ,  H01L21/2885 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.

摘要翻译： 制造晶片级芯片级封装的方法可包括形成穿透IC芯片的芯片焊盘的孔。 基底金属层可以形成在晶片的第一面上以覆盖孔的内表面。 电极金属层可以填充孔并在芯片垫上升起。 可以研磨晶片的第二面，使得孔中的电极金属层可以通过第二面露出。 通过电镀，可以在通过第二面暴露的电极金属层上形成电镀凸块。 可以选择性地去除贱金属层以隔离相邻的电极金属层。 可以沿着划线锯切晶片以将单独的封装与晶片分开。

公开(公告)号：US07524763B2

公开(公告)日：2009-04-28

申请号：US11145994

申请日：2005-06-07

申请人： Soon-Bum Kim ,  Ung-Kwang Kim ,  Keum-Hee Ma ,  Young-Hee Song ,  Sung-Min Sim ,  Se-Yong Oh ,  Kang-Wook Lee ,  Se-Young Jeong

发明人： Soon-Bum Kim ,  Ung-Kwang Kim ,  Keum-Hee Ma ,  Young-Hee Song ,  Sung-Min Sim ,  Se-Yong Oh ,  Kang-Wook Lee ,  Se-Young Jeong

IPC分类号： H01L21/44

CPC分类号： C25D7/12 ,  C25D5/02 ,  H01L21/2885 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.

摘要翻译： 制造晶片级芯片级封装的方法可包括形成穿透IC芯片的芯片焊盘的孔。 基底金属层可以形成在晶片的第一面上以覆盖孔的内表面。 电极金属层可以填充孔并在芯片垫上升起。 可以研磨晶片的第二面，使得孔中的电极金属层可以通过第二面露出。 通过电镀，可以在通过第二面暴露的电极金属层上形成电镀凸块。 可以选择性地去除贱金属层以隔离相邻的电极金属层。 可以沿着划线锯切晶片以将单独的封装与晶片分开。

公开(公告)号：US20050104222A1

公开(公告)日：2005-05-19

申请号：US10944613

申请日：2004-09-20

申请人： Se-Young Jeong ,  Gu-Sung Kim ,  Nam-Seog Kim ,  Gi-Hwan Park ,  Se-Yong Oh ,  Soon-Bum Kim ,  In-Young Lee

发明人： Se-Young Jeong ,  Gu-Sung Kim ,  Nam-Seog Kim ,  Gi-Hwan Park ,  Se-Yong Oh ,  Soon-Bum Kim ,  In-Young Lee

IPC分类号： H01L23/28 ,  H01L21/60 ,  H01L23/16 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H05K3/34 ,  H01L23/48

CPC分类号： H01L24/13 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06102 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29076 ,  H01L2224/30155 ,  H01L2224/30156 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/013

摘要： A flip chip device may have a semiconductor chip with an active surface on which chip pads and a protective layer may be provided. Solder bumps may be provided on the active surface and electrically connected to the chip pads. And a solder bar may be provided on a portion of the protective layer. The solder bar may disperse thermal stress produced in the solder bumps. A metal core may be embedded within the solder bar. The flip chip device may be mounted on and flip-chip bonded to a substrate. The substrate may have land pads to which the solder bumps and the solder bar may be mechanically joined. The solder bar increases a joint area between the flip chip device and the substrate and reinforces solder connections therebetween.

摘要翻译： 倒装芯片器件可以具有其上可以设置有芯片焊盘和保护层的有源表面的半导体芯片。 可以在活性表面上提供焊料凸块并电连接到芯片焊盘。 并且可以在保护层的一部分上设置焊料条。 焊料棒可能会分散焊料凸点产生的热应力。 金属芯可以嵌入在焊条内。 倒装芯片器件可以安装在衬底上并倒装芯片结合到衬底上。 衬底可以具有焊盘，焊盘和焊条可以焊接到其上。 焊条增加了倒装芯片器件和衬底之间的接合面积，并加强了它们之间的焊接连接。

公开(公告)号：US07214604B2

公开(公告)日：2007-05-08

申请号：US10973528

申请日：2004-10-25

申请人： Soon-Bum Kim ,  Se-Young Jeong ,  Se-Yong Oh ,  Nam-Seog Kim

发明人： Soon-Bum Kim ,  Se-Young Jeong ,  Se-Yong Oh ,  Nam-Seog Kim

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1411 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film, each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to complete a flip-chip package. According to the present invention, by employing the three-dimensional structured solder bumps, it is possible to lower the height of the solder bumps, thereby improving the reliability of an ultra thin flip-chip package.

摘要翻译： 提供一种制造超薄倒装芯片封装的方法。 在上述方法中，在半导体芯片的接合焊盘上形成下阻挡金属膜。 在下阻挡金属膜上形成三维结构化的焊料凸块，每个焊料凸块包括设置在棒部的端部的棒部和球部。 包括三维结构的焊料凸块的半导体芯片被结合到印刷电路板上的焊料层以完成倒装芯片封装。 根据本发明，通过采用三维结构化的焊料凸点，可以降低焊锡凸块的高度，从而提高超薄倒装芯片封装的可靠性。

公开(公告)号：US20050090090A1

公开(公告)日：2005-04-28

申请号：US10973528

申请日：2004-10-25

申请人： Soon-Bum Kim ,  Se-Young Jeong ,  Se-Yong Oh ,  Nam-Seog Kim

发明人： Soon-Bum Kim ,  Se-Young Jeong ,  Se-Yong Oh ,  Nam-Seog Kim

IPC分类号： H01L21/60 ,  H01L21/44 ,  H01L23/28 ,  H01L23/48 ,  H01L23/485 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1411 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film, each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to complete a flip-chip package. According to the present invention, by employing the three-dimensional structured solder bumps, it is possible to lower the height of the solder bumps, thereby improving the reliability of an ultra thin flip-chip package.

摘要翻译： 提供一种制造超薄倒装芯片封装的方法。 在上述方法中，在半导体芯片的接合焊盘上形成下阻挡金属膜。 在下阻挡金属膜上形成三维结构化的焊料凸块，每个焊料凸块包括设置在棒部的端部的棒部和球部。 包括三维结构的焊料凸块的半导体芯片被结合到印刷电路板上的焊料层以完成倒装芯片封装。 根据本发明，通过采用三维结构化的焊料凸点，可以降低焊锡凸块的高度，从而提高超薄倒装芯片封装的可靠性。

公开(公告)号：US07824959B2

公开(公告)日：2010-11-02

申请号：US11727760

申请日：2007-03-28

申请人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

发明人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

IPC分类号： H01L21/44

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of forming a wafer level stack structure, including forming a first wafer including a first device chip, wherein the first device chip includes a plurality of input/output (I/O) pads, forming a second wafer including a second device chip, wherein each second device chip contains a second plurality of I/O pads, the second device chip is approximately equal in size to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including a first device chip having a first plurality of input/output (I/O) pads and a second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

摘要翻译： 一种形成晶片级堆叠结构的方法，包括形成包括第一器件芯片的第一晶片，其中所述第一器件芯片包括多个输入/输出（I / O）焊盘，形成包括第二器件芯片的第二晶片， 其中每个第二器件芯片包含第二多个I / O焊盘，所述第二器件芯片的大小与第一芯片尺寸大致相等，堆叠第一晶片和第二晶片，并将第一晶片和第二晶片耦合到每个 其他。 一种形成用于包含晶片级堆叠结构的系统级封装的方法，包括形成晶片级堆叠结构，其包括具有第一多个输入/输出（I / O）焊盘的第一器件芯片和具有第一器件芯片的第二器件芯片， 第二多个I / O焊盘，并且形成连接晶片级堆叠结构的公共电路板。

公开(公告)号：US20050104181A1

公开(公告)日：2005-05-19

申请号：US10899175

申请日：2004-07-27

申请人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

发明人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L23/02

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

公开(公告)号：US20070170576A1

公开(公告)日：2007-07-26

申请号：US11727760

申请日：2007-03-28

申请人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

发明人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

IPC分类号： H01L23/02

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

公开(公告)号：US08278766B2

公开(公告)日：2012-10-02

申请号：US12805321

申请日：2010-07-26

申请人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

发明人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system-in-package, comprising a wafer level stack structure, including at least one first device chip including a first device region having a plurality of input/output(I/O) pads, and at least one second device chip including a second device region having a plurality of input/output(I/O) pads and a second peripheral region surrounding the second device region, wherein the size of the second device region is different from the size of the first device region, wherein the at least one first device chip and the at least one second device chip have approximately equal size; and a common circuit board to which the wafer level stack structure is connected.

摘要翻译： 一种系统级封装，包括晶片级堆叠结构，其包括至少一个包括具有多个输入/输出（I / O）焊盘的第一器件区域的第一器件芯片，以及包括第二器件芯片的至少一个第二器件芯片 器件区域具有多个输入/输出（I / O）焊盘和围绕第二器件区域的第二外围区域，其中第二器件区域的尺寸不同于第一器件区域的尺寸，其中至少一个 第一器件芯片和至少一个第二器件芯片具有大致相等的尺寸; 以及连接晶片级堆叠结构的公共电路板。

公开(公告)号：US20070257350A1

公开(公告)日：2007-11-08

申请号：US11822630

申请日：2007-07-09

申请人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

发明人： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

IPC分类号： H01L23/02

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.