Invention Application
- Patent Title: CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
-
Application No.: US15358852Application Date: 2016-11-22
-
Publication No.: US20170148844A1Publication Date: 2017-05-25
- Inventor: Yen-Shih HO , Hsiao-Lan YEH , Chia-Sheng LIN , Yi-Ming CHANG , Po-Han LEE , Hui-Hsien WU , Jyun-Liang WU , Shu-Ming CHANG , Yu-Lung HUANG , Chien-Min LIN
- Applicant: XINTEC INC.
- Main IPC: H01L27/146
- IPC: H01L27/146 ; H01L21/48 ; H01L21/67 ; H01L23/18
Abstract:
A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.
Public/Granted literature
- US09947716B2 Chip package and manufacturing method thereof Public/Granted day:2018-04-17
Information query
IPC分类:
