公开(公告)号：US20170110495A1

公开(公告)日：2017-04-20

申请号：US15277184

申请日：2016-09-27

Applicant: XINTEC INC.

Inventor： Jyun-Liang WU ,  Chia-Sheng LIN ,  Po-Han LEE ,  Yen-Shih HO

IPC: H01L27/146 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L21/563 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/0231 ,  H01L2224/0237

Abstract: A chip package includes a chip, a dam element, and a height-increasing element. The chip has an image sensing area, a first surface, and a second surface opposite to the first surface. The image sensing area is located on the first surface of the chip. The dam element is located on the first surface of the chip and surrounds the image sensing area. The height-increasing element is located on the dam element, such that the dam element is between the height-increasing element and the chip.

公开(公告)号：US20170148844A1

公开(公告)日：2017-05-25

申请号：US15358852

申请日：2016-11-22

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chien-Min LIN

IPC: H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC classification number: H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.

公开(公告)号：US20170148694A1

公开(公告)日：2017-05-25

申请号：US15358098

申请日：2016-11-21

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU

IPC: H01L23/053 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L21/561 ,  G06K9/0004 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/16225

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.