公开(公告)号：US20170213802A1

公开(公告)日：2017-07-27

申请号：US15481355

申请日：2017-04-06

Applicant: XINTEC INC.

Inventor： Geng-Peng PAN ,  Yi-Ming CHANG ,  Chia-Sheng LIN

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L21/027 ,  H01L21/268

CPC classification number: H01L24/03 ,  H01L21/0273 ,  H01L21/0334 ,  H01L21/268 ,  H01L21/302 ,  H01L21/48 ,  H01L21/481 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03831 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2924/00014

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

公开(公告)号：US20170077158A1

公开(公告)日：2017-03-16

申请号：US15258594

申请日：2016-09-07

Applicant: XINTEC INC.

Inventor： Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yi-Ming CHANG ,  Hsin KUAN

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14685 ,  H01L2224/11

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.

Abstract translation: 提供了包括基板的芯片封装。 基板具有与其相对的第一表面和第二表面。 衬底包括感测区域。 盖板在第一表面上并覆盖感测区域。 屏蔽层覆盖盖板的侧壁并朝向第二表面延伸。 屏蔽层具有与盖板相邻的内表面，并具有远离盖板的外表面。 朝向第二表面延伸的外表面的长度小于朝向第二表面延伸的内表面的长度，并且不小于盖板的侧壁的长度。 还提供了一种形成芯片封装的方法。

公开(公告)号：US20170012081A1

公开(公告)日：2017-01-12

申请号：US15181288

申请日：2016-06-13

Applicant: XINTEC INC.

Inventor： Chia-Lun SHEN ,  Yi-Ming CHANG ,  Hsiao-Lan YEH ,  Yen-Shih HO

IPC: H01L27/146 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L27/14687 ,  H01L21/78 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14636 ,  H01L2224/0331 ,  H01L2224/0332 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/06135 ,  H01L2224/11005 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2224/14179 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17135 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/818 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

Abstract translation: 芯片封装的制造方法包括以下步骤。 将图案化的焊膏层印刷在晶片的图案化导电层上。 多个焊球设置在导电层的第一部分上的焊膏层上。 在焊球和焊膏层上进行回流处理。 从焊膏层的表面转换的焊剂层被清洁。

公开(公告)号：US20160141254A1

公开(公告)日：2016-05-19

申请号：US15008202

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Yi-Min LIN ,  Yi-Ming CHANG ,  Shu-Ming CHANG ,  Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 布置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中的导线层; 位于所述导线层和所述半导体基板之间的绝缘层; 以及设置在所述第一表面上并且具有至少一个孔的金属遮光层，其中所述至少一个孔的形状是四边形。

公开(公告)号：US20150340330A1

公开(公告)日：2015-11-26

申请号：US14715445

申请日：2015-05-18

Applicant: XINTEC INC.

Inventor： Geng-Peng PAN ,  Yi-Ming CHANG ,  Chia-Sheng LIN

IPC: H01L23/00 ,  H01L21/033 ,  H01L21/302 ,  H01L23/48 ,  H01L21/268

CPC classification number: H01L24/03 ,  H01L21/0273 ,  H01L21/0334 ,  H01L21/268 ,  H01L21/302 ,  H01L21/48 ,  H01L21/481 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03831 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2924/00014

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

Abstract translation: 半导体结构的制造方法包括以下步骤。 在晶片衬底的第一表面上形成第一隔离层。 导电焊盘形成在第一隔离层上。 形成穿过第一表面的中空区域和晶片衬底的第二表面，使得第一隔离层通过中空区域露出。 对通过中空区域暴露的第一隔离层进行激光蚀刻处理，使得在第一隔离层中形成第一开口，并且在导电焊盘中形成通过第一开口暴露的凹部。

公开(公告)号：US20150001710A1

公开(公告)日：2015-01-01

申请号：US14315163

申请日：2014-06-25

Applicant: XINTEC INC.

Inventor： Yi-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Ying-Nan WEN

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3171 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06155 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package is provided. The chip package includes a semiconductor chip, an isolation layer, a redistributing metal layer, and at least a bonding pad. The semiconductor chip includes at least one conducting disposed on a surface of the semiconductor chip. The isolation layer is disposed on the surface of the semiconductor chip, wherein the isolation layer has at least one first opening to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has at least a redistributing metal line corresponding to the conducting pad, the redistributing metal line is connected to the first conducting pad through the first opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad to the bonding pad.

Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和至少一个焊盘。 半导体芯片包括设置在半导体芯片的表面上的至少一个导体。 隔离层设置在半导体芯片的表面上，其中隔离层具有至少一个第一开口以暴露第一导电焊盘。 再分配金属层设置在隔离层上，并且至少具有对应于导电焊盘的再分布金属线，再分布金属线通过第一开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘，以将导电焊盘电连接到接合焊盘。

公开(公告)号：US20140264785A1

公开(公告)日：2014-09-18

申请号：US14207224

申请日：2014-03-12

Applicant: XINTEC INC.

Inventor： Yi-Min LIN ,  Yi-Ming CHANG ,  Shu-Ming CHANG ,  Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 布置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中的导线层; 位于所述导线层和所述半导体基板之间的绝缘层; 以及设置在所述第一表面上并且具有至少一个孔的金属遮光层，其中所述至少一个孔的形状是四边形。

公开(公告)号：US20130154077A1

公开(公告)日：2013-06-20

申请号：US13720649

申请日：2012-12-19

Applicant: Xintec Inc.

Inventor： Kuo-Hua LIU ,  Yi-Ming CHANG ,  Hsi-Chien LIN

IPC: H01L21/78 ,  H01L23/48

CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/561 ,  H01L23/10 ,  H01L23/48 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.

Abstract translation: 芯片封装包括：具有第一和第二表面的衬底; 形成在基板上或设置在基板上的器件区域; 设置在所述第一表面上的电介质层; 至少一个导电焊盘，其布置在所述电介质层中并电连接到所述器件区域; 设置在所述电介质层上的平面层，其中所述平面层的上表面与所述导电焊盘之间的垂直距离大于约2μm; 设置在所述第一表面上的透明基板; 设置在所述透明基板和所述平面层之间的第一间隔层; 以及第二间隔层，其设置在所述透明基板和所述基板之间并且延伸到所述电介质层的与所述导电焊盘接触的开口中，其中所述第二间隔层和所述导电焊盘之间基本上没有间隙。

公开(公告)号：US20170148844A1

公开(公告)日：2017-05-25

申请号：US15358852

申请日：2016-11-22

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chien-Min LIN

IPC: H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC classification number: H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.

公开(公告)号：US20150287619A1

公开(公告)日：2015-10-08

申请号：US14676478

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: H01L21/67 ,  H01L21/78 ,  B26F3/00 ,  H01L21/683 ,  H01L21/30

CPC classification number: H01L21/67092 ,  B26D1/095 ,  B26D7/1863 ,  H01L21/6838 ,  Y10T83/0267 ,  Y10T225/10 ,  Y10T225/12 ,  Y10T225/364

Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body. The cap layer is pressed against by the bottom surface of the suction pad and sucked by the suction pad of the vacuum nozzle head after the vacuum pump begins to vacuum the air within the hollow vacuum pipe and the through hole. Then, the first cutter cuts into the interface between the substrate and the cap layer, and the cap lay is separated from the substrate by the suction force of the vacuum nozzle head and the lift force generated by the upward movement of the vacuum nozzle head.

Abstract translation: 本发明的一个实施例提供了一种分离装置，用于分离堆叠制品，例如具有感测功能的半导体芯片封装，包括基板和形成在基板上的盖层。 分离装置包括：真空喷嘴头，包括具有顶表面和底表面的吸盘，穿过吸垫的顶表面和底表面的通孔;以及将通孔连接到真空泵的中空真空管 ; 位于真空喷嘴头下方并基本上与吸盘对准的阶段; 连接到真空喷嘴头以将真空喷嘴头向上或向下提升的控制装置; 以及第一切割器，其包括连接到第一切割体的第一切割体和第一切割刀。 在真空泵开始真空吸入中空真空管和通孔中的空气之后，盖层被吸盘的底面压紧并被真空喷嘴头的吸盘吸入。 然后，第一切割器切入基板和盖层之间的界面，并且通过真空喷嘴头的吸力和由真空喷嘴头的向上运动产生的提升力将盖子与基板分离。