CHIP PACKAGE
    1.
    发明申请

    公开(公告)号:US20210210436A1

    公开(公告)日:2021-07-08

    申请号:US17140964

    申请日:2021-01-04

    Applicant: XINTEC INC.

    Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

    CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权
    芯片包装及其制造方法

    公开(公告)号:US20160111555A1

    公开(公告)日:2016-04-21

    申请号:US14971395

    申请日:2015-12-16

    Applicant: XINTEC INC.

    Abstract: A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips.

    Abstract translation: 制造芯片封装的方法包括提供具有多个半导体芯片的半导体晶片。 在半导体晶片上形成有外隔离物和多个内隔离物。 保护盖形成并设置在外隔离件和内间隔件上。 从其下表面在每个半导体芯片上形成多个空腔,以露出设置在半导体芯片的上表面上的导电焊盘。 形成多个导电部分,并填充每个空腔并电连接到每个导电焊盘。 多个焊球设置在下表面并电连接到每个导电部分。 半导体芯片通过沿着每个半导体芯片之间的多个切割线进行切割来分离。

    CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权
    芯片包装及其制造方法

    公开(公告)号:US20150295097A1

    公开(公告)日:2015-10-15

    申请号:US14682888

    申请日:2015-04-09

    Applicant: XINTEC INC.

    Abstract: A chip package includes semiconductor chips, inner spacers, cavities, conductive portions and solder balls. The semiconductor chip has at least an electronic component and at least an electrically conductive pad disposed on an upper surface thereof. The conductive pad is arranged abreast to one side of the electronic component and electrically connected thereto. The cavities open to a lower surface of the semiconductor chip and extend toward the upper surface to expose the conductive pad on the upper surface. The conductive portions fill the cavities from the lower surface and electrically connected the to conductive pad. The solder balls are disposed on the lower surface and electrically connected to the conductive portions. A gap is created between an outer wall of the inner spacers and an edge of the semiconductor chip.

    Abstract translation: 芯片封装包括半导体芯片,内部间隔件,空腔,导电部分和焊球。 半导体芯片至少具有电子部件,并且至少设置在其上表面上的导电焊盘。 导电焊盘与电子部件的一侧并排设置并与之电连接。 空腔通向半导体芯片的下表面并朝向上表面延伸以暴露上表面上的导电焊盘。 导电部分从下表面填充空腔并电连接到导电垫。 焊球设置在下表面上并电连接到导电部分。 在内隔板的外壁和半导体芯片的边缘之间产生间隙。

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20230230933A1

    公开(公告)日:2023-07-20

    申请号:US18149029

    申请日:2022-12-30

    Applicant: XINTEC INC.

    Abstract: A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.

Patent Agency Ranking