- 专利标题: MEMORY SYSTEM, READING METHOD, PROGRAM, AND MEMORY CONTROLLER
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申请号: US16120093申请日: 2018-08-31
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公开(公告)号: US20190279728A1公开(公告)日: 2019-09-12
- 发明人: Tomoya KODAMA , Takayuki ITOH
- 申请人: TOSHIBA MEMORY CORPORATION
- 优先权: JP2018-041166 20180307
- 主分类号: G11C16/34
- IPC分类号: G11C16/34 ; G11C16/10 ; G11C11/56 ; G11C16/26 ; G11C29/42 ; G11C29/44 ; G11C8/12 ; G06K9/62
摘要:
According to one embodiment, a memory system includes memory cells capable of having data written therein at different write levels. A memory controller is configured to detect first data of the memory cells, then apply a first voltage that is lower than a voltage used for writing the data to the plurality of memory cells, detect second data of the memory cells after the first voltage has been applied, and estimate a write level for the data written to the memory cells based on a comparison of the first data and the second data.
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