公开(公告)号：US20190279728A1

公开(公告)日：2019-09-12

申请号：US16120093

申请日：2018-08-31

申请人： TOSHIBA MEMORY CORPORATION

发明人： Tomoya KODAMA ,  Takayuki ITOH

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  G11C29/42 ,  G11C29/44 ,  G11C8/12 ,  G06K9/62

摘要： According to one embodiment, a memory system includes memory cells capable of having data written therein at different write levels. A memory controller is configured to detect first data of the memory cells, then apply a first voltage that is lower than a voltage used for writing the data to the plurality of memory cells, detect second data of the memory cells after the first voltage has been applied, and estimate a write level for the data written to the memory cells based on a comparison of the first data and the second data.

公开(公告)号：US20190279724A1

公开(公告)日：2019-09-12

申请号：US16119978

申请日：2018-08-31

申请人： TOSHIBA MEMORY CORPORATION

发明人： Takayuki ITOH ,  Tomoya KODAMA

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G06F3/06

摘要： According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first word line including a plurality of first cells and a second word line adjacent to the first word line and including a plurality of second cells. The memory controller determines a read voltage to be used with respect to the plurality of the first cells, according to a plurality of adjacent voltages representing respective threshold voltages of the plurality of the second cells. The memory controller reads data from the first word line using a plurality of determined read voltages.

公开(公告)号：US20180276072A1

公开(公告)日：2018-09-27

申请号：US15703454

申请日：2017-09-13

申请人： Toshiba Memory Corporation

发明人： Tomoya KODAMA ,  Takayuki ITOH ,  Atsushi MATSUMURA ,  Takuya MATSUO

IPC分类号： G06F11/10 ,  G11C16/26 ,  G11C16/04

CPC分类号： G06F11/1068 ,  G06F11/1016 ,  G06F11/1072 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/563

摘要： According to one embodiment, a memory controller includes one or more processors configured to function as a writing unit and a reading unit. The writing unit writes data as threshold voltages of individual memory cells. The reading unit reads the written data by detecting threshold voltages of the individual memory cells. The reading unit includes a selecting unit, a detecting unit, and an estimating unit. The selecting unit selects a read-target memory cell. The detecting unit detects a first threshold voltage at a time of reading of the read-target memory cell, and a second threshold voltage at a time of reading of at least one of adjacent memory cells that are adjacent to the read-target memory cell. The estimating unit estimates a third threshold voltage as a threshold voltage at a time of writing in the read-target memory cell based on the first threshold voltage and the second threshold voltage.