Invention Application
- Patent Title: Cap Layer For Bit Line Resistance Reduction
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Application No.: US16164236Application Date: 2018-10-18
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Publication No.: US20200126996A1Publication Date: 2020-04-23
- Inventor: Priyadarshi Panda , Jianxin Lei , Wenting Hou , Mihaela Baiseanu , Ning Li , Sanjay Natarajan , Gill Yong Lee , In Seok Hwang , Nobuyuki Sasaki , Sung-Kwan Kang
- Applicant: Applied Materials, Inc.
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L21/033 ; H01L21/3213

Abstract:
Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.
Public/Granted literature
- US10700072B2 Cap layer for bit line resistance reduction Public/Granted day:2020-06-30
Information query
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