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公开(公告)号：US11171141B2
公开(公告)日：2021-11-09
申请号：US16804226
申请日：2020-02-28
发明人： Priyadarshi Panda , Seshadri Ganguli , Sang Ho Yu , Sung-Kwan Kang , Gill Yong Lee , Sanjay Natarajan , Rajib Lochan Swain , Jorge Pablo Fernandez
IPC分类号： H01L27/108
摘要： Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
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公开(公告)号：US11631680B2
公开(公告)日：2023-04-18
申请号：US17096099
申请日：2020-11-12
发明人： Priyadarshi Panda , In Seok Hwang
IPC分类号： H01L27/108 , H01L21/768 , C23C28/00 , H01L21/285 , H01L21/02
摘要： A process of smoothing a top surface of a bit line metal of a memory structure to decrease resistance of a bit line stack. The process includes depositing titanium layer of approximately 30 angstroms to 50 angstroms on polysilicon layer on a substrate, depositing first titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on titanium layer, annealing substrate at a temperature of approximately 700 degrees Celsius to approximately 850 degrees Celsius, depositing second titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on first titanium nitride layer after annealing, depositing a bit line metal layer of ruthenium on second titanium nitride layer, annealing bit line metal layer at temperature of approximately 550 degrees Celsius to approximately 650 degrees Celsius, and soaking bit line metal layer in hydrogen-based ambient for approximately 3 minutes to approximately 6 minutes during annealing.
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公开(公告)号：US11621266B2
公开(公告)日：2023-04-04
申请号：US17522448
申请日：2021-11-09
发明人： Priyadarshi Panda , Seshadri Ganguli , Sang Ho Yu , Sung-Kwan Kang , Gill Yong Lee , Sanjay Natarajan , Rajib Lochan Swain , Jorge Pablo Fernandez
IPC分类号： H01L21/67 , H01L27/108
摘要： Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
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公开(公告)号：US11751382B2
公开(公告)日：2023-09-05
申请号：US17717582
申请日：2022-04-11
发明人： Lequn Liu , Priyadarshi Panda , Jonathan C. Shaw
CPC分类号： H10B12/482 , H01L21/67167 , H01L21/67213
摘要： Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
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公开(公告)号：US11329052B2
公开(公告)日：2022-05-10
申请号：US16939361
申请日：2020-07-27
发明人： Lequn Liu , Priyadarshi Panda , Jonathan C. Shaw
IPC分类号： H01L27/108 , H01L21/67
摘要： Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
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公开(公告)号：US20210035982A1
公开(公告)日：2021-02-04
申请号：US16939361
申请日：2020-07-27
发明人： Lequn Liu , Priyadarshi Panda , Jonathan C. Shaw
IPC分类号： H01L27/108 , H01L21/67
摘要： Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
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公开(公告)号：US20200235104A1
公开(公告)日：2020-07-23
申请号：US16839392
申请日：2020-04-03
发明人： Priyadarshi Panda , Jianxin Lei , Wenting Hou , Mihaela Balseanu , Ning Li , Sanjay Natarajan , Gill Yong Lee , In Seok Hwang , Nobuyuki Sasaki , Sung-Kwan Kang
IPC分类号： H01L27/108 , H01L21/3213 , H01L21/033
摘要： Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.
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公开(公告)号：US20220238533A1
公开(公告)日：2022-07-28
申请号：US17717582
申请日：2022-04-11
发明人： Lequn Liu , Priyadarshi Panda , Jonathan C. Shaw
IPC分类号： H01L27/108 , H01L21/67
摘要： Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
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公开(公告)号：US20220165593A1
公开(公告)日：2022-05-26
申请号：US17103847
申请日：2020-11-24
IPC分类号： H01L21/67 , H01L27/108 , G06N3/08
摘要： A method of forming a multi-layer stack on a substrate comprises: processing a substrate in a first process chamber using a first deposition process to deposit a first layer of a multi-layer stack on the substrate; removing the substrate from the first process chamber; measuring a first thickness of the first layer using an optical sensor; determining, based on the first thickness of the first layer, a target second thickness for a second layer of the multi-layer stack; determining one or more process parameter values for a second deposition process that will achieve the second target thickness for the second layer; and processing the substrate in a second process chamber using the second deposition process with the one or more process parameter values to deposit the second layer of the multi-layer stack approximately having the target second thickness over the first layer.
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公开(公告)号：US20220165541A1
公开(公告)日：2022-05-26
申请号：US17103845
申请日：2020-11-24
摘要： A substrate processing system comprises an etch chamber configured to perform an etch process on a substrate, the etch chamber comprising an optical sensor to generate one or more optical measurements of a film on the substrate during and/or after the etch process. The system further comprises a computing device operatively connected to the etch chamber, wherein the computing device is to: receive the one or more optical measurements of the film; determine, for each optical measurement of the one or more optical measurements, a film thickness of the film; determine an etch rate of the film based on the one or more optical measurements using the determined film thickness of each optical measurement of the one or more optical measurements; and determine a process parameter value of at least one process parameter for a previously performed process that was performed on the substrate based on the etch rate.
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